Motorola PowerQUICC II MPC8280 Series Reference Manual page 393

9.12.1 Message Registers
The PCI bridge contains two inbound message registers and two outbound message
registers. The registers are each 32 bits. The inbound registers allow a remote host or PCI
master to write a 32-bit value which in turn causes an interrupt to the local processor that
implements the PowerPC architecture because the register indirectly drives an interrupt line
to the local processor. The outbound register allows the local processor to write an
outbound message which, in turn, causes the outbound interrupt signal INTA to assert.
The interrupt to the local processor is cleared by setting the appropriate bit in the inbound
message interrupt status register. The interrupt to PCI (INTA) is cleared by setting the
appropriate bit in the outbound interrupt status register.
9.12.1.1 Inbound Message Registers (IMRx)
The inbound message registers, described in Figure 9-60 and Figure 9-46, are accessible
from the PCI bus and the 60x bus in both host and agent modes.
31
Field
Reset
R/W
Addr
15
Field
Reset
R/W
Addr
Figure 9-60. Inbound Message Registers (IMRx)
Bits Name
31–0 IMSGx
9.12.1.2 Outbound Message Registers (OMRx)
The outbound message registers, described in Figure 9-61 and Figure 9-47, are accessible
from the PCI bus and the 60x bus in both host and agent modes.
MOTOROLA
Freescale Semiconductor, Inc.
Undefined
0x10452 (IMR0); 0x10456 (IMR1)
Undefined
0x10450 (IMR0); 0x10454 (IMR1)
Table 9-46. IMRx Field Descriptions
Inbound message x. Contains generic data to be passed between the local
processor and external hosts.
Chapter 9. PCI Bridge
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IMSGx
R/W
IMSGx
R/W
Description
Message Unit (I O)
2
16
0
9-71