Table of Contents
Advertisement
CC11x1-Q1
SWRS076B – 11-07-22-013 - APRIL 2009 – REVISED APRIL 2010
Although CC11x1-Q1 has a balanced RF input/output, the chip can be connected to a single-ended
antenna with few external low cost capacitors and inductors.
The passive matching/filtering network connected to CC11x1-Q1 should have the following differential
impedance as seen from the RF-port (RF_P and RF_N) toward the antenna:
Z
= 122 + j31 Ω
out 315 MHz
Z
= 116 + j41 Ω
out 433 MHz
Z
out 868/915 MHz
To ensure optimal matching of the CC11x1-Q1 differential output it is recommended to follow the
reference design as closely as possible. Gerber files for the reference designs are available for download
from the TI web site.
3.24 PCB Layout Recommendations
The top layer should be used for signal routing, and the open areas should be filled with metallization
connected to ground using several vias.
The area under the chip is used for grounding and shall be connected to the bottom ground plane with
several vias. In the reference designs, five vias are placed inside the exposed die attached pad. These
vias should be tented (covered with solder mask) on the component side of the PCB to avoid migration of
solder through the vias during the solder reflow process.
The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process,
which may cause defects (splattering, solder balling). Using "tented" vias reduces the solder paste
coverage below 100%.
Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to
decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate
vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the
CC11x1-Q1 supply pin. Supply power filtering is very important.
Each decoupling capacitor ground pad should be connected to the ground plane using a separate via.
Direct connections between neighboring power pins increase noise coupling and should be avoided
unless absolutely necessary.
The external components ideally should be as small as possible (0402 is recommended) and surface
mount devices are highly recommended. Please note that components smaller than those specified may
have differing characteristics.
Precaution should be used when placing the microcontroller to avoid noise interfering with the RF circuitry.
A development kit with a fully assembled evaluation module is available. It is strongly advised that this
reference layout is followed closely to get the best performance. The schematic, BOM, and layout Gerber
files are all available from the TI web site.
3.25 General Purpose / Test Output Control Pins
The three digital output pins GDO0, GDO1, and GDO2 are general control pins configured with
IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO3_CFG respectively.
the different signals that can be monitored on the GDO pins. These signals can be used as inputs to the
MCU. GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin
is valid only when CS is high. The default value for GDO1 is 3-stated, which is useful when the SPI
interface is shared with other devices.
The default value for GDO0 is a 135-141 kHz clock output (XOSC frequency divided by 192). Because the
XOSC is turned on at power-on-reset, this can be used to clock the MCU in systems with only one crystal.
When the MCU is up and running, it can change the clock frequency by writing to IOCFG0.GDO0_CFG.
56
Detailed Description
= 86.5 + j43 Ω
Submit Documentation Feedback
Table 3-17
Copyright © 2009–2010, Texas Instruments Incorporated
www.ti.com
shows
Advertisement
Table of Contents
