Conflict Between Tcmicr Read And Input Capture; Conflict Between Edge Detection In Cycle Measurement Mode And Writing To Tcmmlcm Or Tcmmincm - Renesas H8S/2100 Series Hardware Manual

Section 11 16-Bit Cycle Measurement Timer (TCM)
11.6.3

Conflict between TCMICR Read and Input Capture

When operation is in timer mode and the corresponding input capture signal is detected during
reading of TCMICR, the input capture signal is delayed by one system clock (φ). Figure 11.15
shows the timing of this conflict.
φ
TCMCYI
TCMICR
read signal
Input capture
signal
TCMCNT
TCMICR
ICPF
Figure 11.15 Conflict between TCMICR Read and Input Capture
11.6.4 Conflict between Edge Detection in Cycle Measurement Mode and Writing to
TCMMLCM or TCMMINCM
If the selected edge of TCMCYI is detected in the second half of a cycle of writing to the register
(TCMMLCM or TCMMINCM) in cycle measurement mode, the detected edge signal is delayed
by one cycle of the system clock (φ).
Figure 11.16 shows the timing of this conflict.
φ
TCMCYI
Internal write
signal
Input capture
signal
TCMCNT
TCMICR
MAXOVF
Figure 11.16 Conflict between Edge Detection and Register Write
Rev. 1.00 Apr. 28, 2008 Page 326 of 994
REJ09B0452-0100
N - 1 N Capture generated
M
N
M
(Cycle Measurement Mode)
Capture generated
TCMICR > TCMCNT (Upper liit over)
N + 1
N
H'0000
N
N + 2