Channel Priority And Dma Transfer Timing - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

5. Channel Priority and DMA Transfer Timing

If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
BCLK), the DMAS bit on each channel is set to "1" (DMA requested) at the same time. In this case, the
DMA requests are arbitrated according to the channel priority, DMA0 > DMA1.
The following describes DMAC operation when DMA0 and DMA1 requests are detected active in the
same sampling period.
Figure 1.12.6 shows an example of DMA transfer effected by external factors.
In Figure 1.12.6, DMA0 request having priority is received first to start a transfer when a DMA0 request
and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, a bus arbitra-
tion is returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After
one DMA1 transfer is completed, the bus arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 1.12.6, occurs more than one time, the DMAS bit is set to "0" as soon
as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
__________
Refer to "(7) HOLD Signal in Bus Control" for details about bus arbitration between the CPU and DMA.
An example where DMA requests for external causes are detected active at the same time,
a DMA transfer is executed in the shortest cycle.
BCLK
DMA0
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 1.12.6 DMA Transfer by External Factors
Rev.1.00 2003.05.30 page 96
DMAC
Bus arbitration