Dma Channel Prioritization - Analog Devices ADSP-2106x SHARC User Manual

When a particular I/O port needs to write data to internal memory, it
asserts its request. This request is prioritized with all other valid DMA
requests. See Figure 6.2.
When a channel becomes the highest priority requester, its internal
grant is asserted by the DMA controller. In the next clock cycle, the
DMA transfer is started. When an I/O port wishes to read data from
internal memory, the sequence is the same.
If a DMA channel is disabled, no grants will be given for that channel,
regardless of whether it has data to transfer.
6.3.3

DMA Channel Prioritization

Since more than one DMA channel may have a request active in a
particular cycle, a prioritization scheme is used to select the channel to
service. Prioritization is needed to determine which channel can use
the IOD (I/O Data) bus to access memory. The ADSP-2106x always
uses a fixed prioritization (except for the external port DMA channels,
as described below). Table 6.13 lists in descending order of priority the
possible I/O bus accesses including DMA channels .
– Core Accesses to DA Group Registers
Channel 0 – Serial Port 0 Receive
Channel 1 – Serial Port 1 Receive (or Link Buffer 0)
Channel 2 – Serial Port 0 Transmit
Channel 3 – Serial Port 1 Transmit (or Link Buffer 1)
– TCB Chain Loading Requests
– External Accesses of Internal Memory (Direct Reads, Direct Writes)
3
Channel 4 – Link Buffer 2
3
Channel 5 – Link Buffer 3
Channel 6 – Ext. Port Buffer 0 (or Link Buffer 4)
Channel 7 – Ext. Port Buffer 1 (or Link Buffer 5)
Channel 8 – Ext. Port Buffer 2
Channel 9 – Ext. Port Buffer 3
Table 6.13 Internal Memory I/O Bus Access Priority
1. TCB chain loading uses the I/O bus and therefore requires prioritization. (See
"DMA Chaining" below.)
2. Direct reads and writes use the I/O bus and therefore require prioritization.
(See "Direct Writes" and "Direct Reads" in the Host Interface chapter.)
3. These DMA channels are not available on the ADSP-21061
4. Rotating priority can be selected for External Port Buffers.
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HIGHEST PRIORITY
1
4
4
3, 4
3, 4
LOWEST PRIORITY
DMA 6
2
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