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7.5.7 DMA restart register (DRST)
This register is used to restart a DMA transfer that was forcibly interrupted by inputting an IDMASTP signal. The
ENn bits of this register are linked respectively with the ENn bits of the DCHCn registers (n = 0 to 3). After a DMA
transfer was forcibly interrupted by inputting the IDMASTP signal, the DMA channel for which the transfer was
interrupted is confirmed from the contents of the DDIS register, and the DMA transfer can be restarted by setting (1)
the ENn bit of the corresponding DMA channel.
This register can be read or written in 8-bit or 1-bit units.
7
6
DRST
0
0
Bit position
Bit name
3 to 0
EN3 to
EN0
Caution Bits 7 to 4 of the DRST register must be set to 0. The operation when these bits are set to 1
is not guaranteed.
Remark
n = 0 to 3
CHAPTER 7 DMAC
Figure 7-9. DMA Restart Register (DRST)
5
4
0
0
EN3
Sets whether DMA transfer is enabled or disabled for DMA channel n. This bit is cleared (0)
when the DMA transfer ends due to the output of a terminal count. It is also cleared (0) when an
IDMASTP signal is input or when DMA transfer is forcibly terminated by setting (1) the INITn bit
of the DCHCn register.
0: DMA transfer is disabled
1: DMA transfer is enabled
Preliminary User's Manual A14874EJ3V0UM
3
2
1
EN2
EN1
Function
0
Address
After reset
EN0
FFFFF0F2H
00H
161
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