Multiprocessing; I/O Processor; Serial Ports - Analog Devices ADSP-2106x SHARC User Manual

1 Introduction
1.3.5

Multiprocessing

The ADSP-2106x offers powerful features tailored to multiprocessing
DSP systems. The unified address space allows direct interprocessor
accesses of each ADSP-2106x's internal memory. Distributed bus
arbitration logic is included on-chip for simple, glueless connection of
systems containing up to six ADSP-2106xs and a host processor.
Master processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Processor
bus lock allows indivisible read-modify-write sequences for semaphores.
A vector interrupt capability is provided for interprocessor commands.
Maximum throughput for interprocessor data transfer is
240 Mbytes/sec over the link ports or external port. Broadcast writes
allow simultaneous transmission of data to all ADSP-2106xs and can
be used to implement reflective semaphores.
1.3.6

I/O Processor

The ADSP-2106x's I/O Processor (IOP) includes two serial ports, six
4-bit link ports, and a DMA controller.

1.3.6.1 Serial Ports

The ADSP-2106x features two synchronous serial ports that provide an
inexpensive interface to a wide variety of digital and mixed-signal
peripheral devices. The serial ports can operate at the full clock rate of
the processor, providing each with a maximum data rate of 40 Mbit/s.
Independent transmit and receive functions provide greater flexibility
for serial communications. Serial port data can be automatically
transferred to and from on-chip memory via DMA. Each of the serial
ports offers a TDM multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 to 32 bits.
They offer selectable synchronization and transmit modes as well as
optional µ-law or A-law companding. Serial port clocks and frame
syncs can be internally or externally generated.
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