Clock Specifications - Texas Instruments MSPM0G350 Series Manual

MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
SLASF88 – OCTOBER 2023
(3) The start-up time is measured from the time that VDD crosses VBOR0- (cold start-up) to the time that the first instruction of the user
program is executed.

7.9 Clock Specifications

7.9.1 System Oscillator (SYSOSC)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Factory trimmed SYSOSC frequency
f
SYSOSC
User trimmed SYSOSC frequency
SYSOSC frequency accuracy when
frequency correction loop (FCL) is
f
SYSOSC
enabled and an ideal ROSC resistor is
(1) (2)
assumed
SYSOSC accuracy when frequency
correction loop (FCL) is enabled with
f
SYSOSC
R resistor put at R
OSC
trimmed frequencies
SYSOSC frequency accuracy when
frequency correction loop (FCL) is
f
SYSOSC
enabled when the internal ROSC resistor
(4)
is used
SYSOSC accuracy when frequency
f
SYSOSC
correction loop (FCL) is disabled, 32MHz
SYSOSC accuracy when frequency
f correction loop (FCL) is disabled, for
SYSOSC
factory trimmed frequencies, 4MHz
External resistor put between ROSC pin
f
SYSOSC
(1)
and VSS
f Settling time to target accuracy
SYSOSC
f additional undershoot accuracy
SYSOSC
f
SYSOSC (3)
during t
settle
(1) The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an external reference resistor (R
be connected between the device ROSC pin and VSS when using the FCL. Accuracies are shown for a ±0.1% ±25ppm R
tolerance resistors may also be used (with reduced SYSOSC accuracy). See the SYSOSC section of the technical reference manual
for details on computing SYSOSC accuracy for various R
enabled.
(2) Represents the device accuracy only. The tolerance and temperature drift of the ROSC resistor used must be combined with this spec
to determine final accuracy. Performance for a ±0.1% ±25ppm R
(3) When SYSOSC is waking up (for example, when exiting a low power mode) and FCL is enabled, the SYSOSC will initially undershoot
the target frequency f
SYSOSC
achieved.
(4) The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an internal reference resistor when using the
FCL. See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy.
34 Submit Document Feedback
SYSOSCCFG.FREQ=00 (BASE)
SYSOSCCFG.FREQ=01
SYSOSCCFG.FREQ=10,
SYSOSCTRIMUSER.FREQ=10
SYSOSCCFG.FREQ=10,
SYSOSCTRIMUSER.FREQ=01
SETUSEFCL=1, T
SETUSEFCL=1, -40 ℃ ≤ T
SETUSEFCL=1, -40 ℃ ≤ T
SETUSEFCL=1, -40 ℃ ≤ T
SETUSEFCL=1, T
±25ppm R
SETUSEFCL=1, -40 ℃ ≤ T
℃, ±0.1% ±25ppm R
pin, for factory
SETUSEFCL=1, -40 ℃ ≤ T
OSC
(1)
℃, ±0.1% ±25ppm R
SETUSEFCL=1, -40 ℃ ≤ T
±0.1% ±25ppm R
SETUSEFCL=1 -40 ℃ ≤ T
SETUSEFCL=0,
SYSOSCCFG.FREQ=00, -40 ℃ ≤ T
125 ℃
SETUSEFCL=0,
SYSOSCCFG.FREQ=01, -40 ℃ ≤ T
125 ℃
SETUSEFCL=1
(3)
SETUSEFCL=1, ±0.1% 25ppm R
SETUSEFCL=1, ±0.1% 25ppm R
by an additional error of up to f
Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
TEST CONDITIONS
= 25 ℃
a
≤ 85 ℃
a
≤ 105 ℃
a
≤ 125 ℃
a
= 25 ℃, ±0.1%
a
OSC
≤ 85
a
OSC
≤ 105
a
OSC
≤ 125 ℃,
a
OSC
≤ 125 ℃
a
≤
a
≤
a
(1)
OSC
(1)
OSC
accuracies. R does not need to be populated if the FCL is not
OSC OSC
is given as a reference point.
OSC
for the time t
settle,SYSOSC settle,SYSOSC
www.ti.com
MIN TYP MAX
32
4
24
16
-0.41 0.58
-0.80 0.93
-0.80 1.09
-0.80 1.30
-0.5 0.7
-1.1 1.2
-1.1 1.4
-1.1 1.7
-1.4 1.8
-2.6 1.8
-2.7 2.3
100
30
-11
) which must
OSC
OSC
, after which the target accuracy is
Copyright © 2023 Texas Instruments Incorporated
UNIT
MHz
%
%
%
%
kΩ
us
%
; relaxed