Appendix A Cpu Instruction Set; Instructions - Renesas H8 Series Hardware Manual

A.1

Instructions

Operation Notation
Rd8/16
Rs8/16
Rn8/16
CCR
N
Z
V
C
PC
SP
#xx: 3/8/16
d: 8/16
@aa: 8/16
+
–
×
÷
∧
∨
⊕
→
—
Condition Code Notation
Symbol
*
0
—

Appendix A CPU Instruction Set

General register (destination) (8 or 16 bits)
General register (source) (8 or 16 bits)
General register (8 or 16 bits)
Condition code register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
Stack pointer
Immediate data (3, 8, or 16 bits)
Displacement (8 or 16 bits)
Absolute address (8 or 16 bits)
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
Exclusive logical OR
Move
Logical complement
Modified according to the instruction result
Not fixed (value not guaranteed)
Always cleared to 0
Not affected by the instruction execution result
Appendix A CPU Instruction Set
Rev. 7.00 Mar 10, 2005 page 535 of 652
REJ09B0042-0700