Stop Signal; Repeated Start - Freescale Semiconductor MCF54455 Reference Manual

2
I C Interface
33.3.4 Acknowledge
The transmitter releases the I2C_SDA line high during the acknowledge clock pulse as shown in
Figure 33-9. The receiver pulls down the I2C_SDA line during the acknowledge clock pulse so that it
remains stable low during the high period of the clock pulse.
If it does not acknowledge the master, the slave receiver must leave I2C_SDA high. The master can then
generate a STOP signal to abort data transfer or generate a START signal (repeated start, shown in
Figure 33-10 and discussed in
I2C_SCL
I2C_SDA by Transmitter
I2C_SDA by Receiver
If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means
end-of-data to the slave. The slave releases I2C_SDA for the master to generate a STOP or START signal
(Figure 33-9).
33.3.5

STOP Signal

The master can terminate communication by generating a STOP signal to free the bus. A STOP signal is
defined as a low-to-high transition of I2C_SDA while I2C_SCL is at logical high (see F in
The master can generate a STOP even if the slave has generated an acknowledgment, at which point the
slave must release the bus. The master may also generate a START signal following a calling address,
without first generating a STOP signal. Refer to
33.3.6

Repeated START

A repeated START signal is a START signal generated without first generating a STOP signal to terminate
the communication, as shown in
another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.
33-9
Section 33.3.6, "Repeated
1 2 3
Bit7 Bit6 Bit5
START Signal
Figure 33-9. Acknowledgement by Receiver
Section 33.3.6, "Repeated START."
Figure 33-10. The master uses a repeated START to communicate with
START") to start a new calling sequence.
4 5 6 7 8
Bit0
Bit4 Bit3 Bit2 Bit1
R/W
ACK
9
Figure 33-7).
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