Freescale Semiconductor MCF54455 Reference Manual page 470

Figure 20-9 shows the write cycle timing diagram.
The address and data busses are muxed between the FlexBus and PCI
controller. At the end of the write bus cycles, the address signals are
indeterminate.
Mux'd Bus
Non-Mux'd Bus
FB_CSn, FB_BE/BWEn
20.4.6.3 Bus Cycle Sizing
This section shows timing diagrams for various port size scenarios.
read transfer to an 8-bit device with no wait states. The address is driven on the full FB_AD[
the first clock. The device tristates FB_AD[
Freescale Semiconductor
NOTE
S0
FB_CLK
FB_AD[Y:0]
FB_AD[31:X]
ADDR[31:X]
FB_A[23:0]
ADDR[31:X]
FB_D[31:X]
FB_R/W
FB_ALE
FB_OE
FB_TA
FB_TSIZ[1:0]
Figure 20-9. Basic Write-Bus Cycle
31:24] on the second clock and continues to drive address on
S1 S2 S3
ADDR[Y:0]
DATA
ADDR[23:0]
DATA
TSIZ[1:0]
Figure 20-10
FlexBus
S0
illustrates the basic byte
31:8 ] bus in
20-17