Modes Of Operation - Freescale Semiconductor MCF54455 Reference Manual

– FIFO overrun (logical OR of RX overflow and TX underflow interrupts)
– General DSPI interrupt (logical OR of the seven above conditions)
• Modified SPI transfer formats for communication with slower peripheral devices
• Continuous serial communications clock (DSPI_SCK)
31.1.4

Modes of Operation

The DSPI module has four available distinct modes:
• Master mode
• Slave mode
• Module disable mode
• Debug mode
Master, slave, and module disable modes are module-specific modes while debug mode is a
device-specific mode.
Bits in the DSPI_MCR register determine the module-specific modes. Debug mode is a mode that the
entire device can enter in parallel with the DSPI being configured in one of its module-specific modes.
31.1.4.1 Master Mode
In master mode, the DSPI can initiate communications with peripheral devices. The DSPI operates as bus
master when the DSPI_MCR[MSTR] bit is set. The serial communications clock (DSPI_SCK) is
controlled by the master DSPI.
Master mode transfer attributes are controlled by the SPI command in the current TX FIFO entry. The
CTAS field in the SPI command selects which of the eight DSPI_CTARs sets the transfer attributes.
Transfer attribute control is on a frame by frame basis. See
(SPI) Configuration" for more details.
31.1.4.2 Slave Mode
In slave mode, the DSPI responds to transfers initiated by an SPI master. The DSPI operates as bus slave
when the DSPI_MCR[MSTR] bit is cleared. A bus master selects the DSPI slave by having the slave's
DSPI_SS signal asserted. In slave mode, the bus master provides DSPI_SCK. The bus master controls all
transfer attributes, but clock polarity, clock phase, and numbers of bits to transfer must be configured in
the DSPI slave for proper communications.
In slave mode, data transfers MSB first. The LSBFE field of the associated CTAR register is ignored.
31.1.4.3 Module Disable Mode
The module disable mode is used for MCU power management. The clock to the non-memory mapped
logic in the DSPI stops while in module disable mode. The DSPI enters the module disable mode when
the DSPI_MCR[MDIS] bit is set. See
module disable mode.
Freescale Semiconductor
Section 31.4.2, "Serial Peripheral Interface
Section 31.4.7, "Power Saving
DMA Serial Peripheral Interface (DSPI)
Features," for more details on the
31-3