Freescale Semiconductor MCF54455 Reference Manual page 920

Chapter
Rearranged sections
Corrected RTS instruction's PST definition in PSTDDATA Specification for User-Mode Instructions table
Corrected "and and" to "&&" in the logical expressions throughout.
Debug
Changed ATTR to AATR in AATR field descriptions
Module
Changed PBAC address from DRc=0x04 to 0x0A.
Added note to TDR section: "When performing a level-1, level-2, and level-1 breakpoint sequence, TDR[29] must be
cleared in the level-2 breakpoint handler for the second level-1 breakpoint to occur."
Changed reset value of IDCODE[DC] to see note, and added note that this value varies, depending on design center
JTAG
location.
A.3 Changes Between Rev. 4 and Rev. 5
Chapter
Rescinded previous change. The 256-pin devices (MCF54450 and MCF54451) do not contain the PCI bus
Throughout
controller.
Corrected timing diagrams for bursting in multiplexed AD mode. The address on FB_AD does not increment, only
FlexBus
the starting address is available during the first bus cycle on FB_AD.
Changed note at beginning of chapter that the MCF54450 and MCF54451 devices do not contain a PCI bus
PCI
controller
A.4 Changes Between Rev. 5 and Rev. 6
Chapter
CCM) Added part identification number to description of PIN field in Chip Identification Register.
FlexBus Corrected description of BAM field in CSMRn field description table.
The "SLE SRE URE AAE SEE FRE PCE UEE UE" bits in the USBINTR register were corrected to read-write. They
SDRAMC
had been shown as write one to clear.
UART UART Status Register bit 3 corrected from "TEMP" to "TXEMP" in field description table.
SDRAMC Made changes to Layout Considerations section because MCF54455 has a true SSTL pad.
Cache Changed the ACRn register diagram to show the SP bit as write-only.
Freescale Semiconductor
Table A-2. Rev. 3 to Rev. 4 Changes (continued)
Description
Table A-3. Rev. 4 to Rev. 5 Changes
Description
Table A-4. Rev. 5 to Rev. 6 Changes
Description
Revision History
A-5