Power Management - Freescale Semiconductor MCF54455 Reference Manual

move.l #RAMBASE+RAMVALID,D0
movec.l D0, RAMBAR
The following loop initializes the entire SRAM to zero:
lea.l RAMBASE,A0
move.l #8192,D0
SRAM_INIT_LOOP:
clr.l (A0)+
clr.l (A0)+
clr.l (A0)+
clr.l (A0)+
subq.l #4,D0
bne.b SRAM_INIT_LOOP
7.3.2

Power Management

As noted previously, depending on the RAMBAR-defined configuration, instruction fetch and operand
read accesses may be sent to the SRAM and cache simultaneously. If the access maps to the SRAM
module, it sources the read data and the cache access is discarded. If the SRAM is used only for data
operands, setting the ASn bits associated with instruction fetches can decrease power dissipation.
Additionally, if the SRAM contains only instructions, masking operand accesses can reduce power
dissipation. Table 7-3 shows examples of typical RAMBAR settings.
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;load RAMBASE + valid bit into D0.
;load RAMBAR and enable SRAM
;load pointer to SRAM
;load loop counter into D0 (SRAM size/4)
;clear 4 bytes of SRAM
;clear 4 bytes of SRAM
;clear 4 bytes of SRAM
;clear 4 bytes of SRAM
;decrement loop counter
;if done, then exit; else continue looping
Table 7-3. Typical RAMBAR Setting Examples
Data Contained in SRAM
Instruction Only
Data Only
Instructions and Data
RAMBAR[7:0]
0x2B
0x35
0x21
Static RAM (SRAM)
7-5