Freescale Semiconductor MCF54455 Reference Manual page 378

16.3.5.10 FEC/I2C Pin Assignment Register (PAR_FECI2C)
The PAR_FECI2C register controls the functions of the I
Address: 0xFC0A_406A (PAR_FECI2C)
15 14 13
R 0 0 0
W
Reset 0 0 0
Field
15–12 Reserved, should be cleared.
11–10 FEC1 MDIO and MDC pin assignment. These bit fields configure the FEC1_MDC and FEC1_MDIO pins for one of
PAR_MDC1 their primary functions or GPIO.
9–8
PAR_MDIO1
7 Reserved, should be cleared.
6 FEC0 MDC pin assignment.
PAR_MDC0 0 FEC0_MDC pin configured for GPIO
1 FEC0_MDC pin configured for FEC0 management data clock function
5 Reserved, should be cleared.
4 FEC0 MDIO pin assignment.
PAR_MDIO0 0 FEC0_MDIO pin configured for GPIO
1 FEC0_MDIO pin configured for FEC0 management data function
3–2 I2C_SCL and I2C_SDA pin assignment. These bit fields configure the I2C_SCL and I2C_SDA pins for one of their
PAR_SCL primary functions or GPIO.
1–0
PAR_SDA
Freescale Semiconductor
12 11 10 9
0
PAR_MDC1 PAR_MDIO1
0 0 0 0
Figure 16-43. FEC/I2C Pin Assignment (PAR_FECI2C)
Table 16-18. PAR_FECI2C Field Descriptions
PAR_MDC1
00
01 Reserved
10 ATA_DIOR
11 FEC_MDC
PAR_SCL
00
01
10 Reserved
11 I2C_SCL
2
C and the FEC MDC and MDIO pins.
8 7 6 5
0 0
PAR_
MDC0
0 0 0 0
Description
PAR_MDIO1
GPIO GPIO
Reserved
ATA_DIOW
FEC_MDIO
PAR_SDA
GPIO GPIO
U2TXD U2RXD
Reserved
I2C_SDA
Pin Multiplexing and Control
Access: User read/write
4 3 2 1
PAR_
PAR_SCL PAR_SDA
MDIO0
0 0 0 0
0
0
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