Basic Read Bus Cycle - Freescale Semiconductor MCF54455 Reference Manual

20.4.6.1

Basic Read Bus Cycle

During a read cycle, the ColdFire device receives data from memory or a peripheral device.
is a read cycle flowchart.
Throughout this chapter FB_AD[31:X] indicates a 32-, 16-, or 8-bit wide
data bus. FB_AD[
width.
1. Set FB_R/W to read.
2. Place address on FB_AD[31:0].
3. Assert FB_ALE.
1. Negate FB_ALE.
2. Assert FB_CSn.
1.
FlexBus asserts internal FB_TA
(auto-acknowledge/internal termination).
2. Sample FB_TA low and latch data.
1. Start next cycle.
The read cycle timing diagram is shown in
In the next set of timing diagrams, the dotted lines indicate FB_TA, FB_OE,
and FB_CSn timing when internal termination is used (CSCR[AA] = 1).
The external and internal FB_TA assert at the same time; however, FB_TA
is not driven externally for internally-terminated bus cycles.
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this beneficial.
The address and data busses are muxed between the FlexBus and PCI
controller. At the end of the read bus cycles the address signals are
indeterminate.
Freescale Semiconductor
NOTE
] is an address bus that can be
Y:0
ColdFire device
Figure 20-6. Read Cycle Flowchart
Figure
NOTE
NOTE
32-, 24-, or 16
System
1. Decode address.
1. Select the appropriate slave device.
2. Drive data on FB_AD[31:X].
3. Assert FB_TA (external termination).
1. Negate FB_TA (external termination).
20-7.
FlexBus
Figure 20-6
-bits in
20-15