Freescale Semiconductor MCF54455 Reference Manual page 526

Field
22 Reserved. Fixed to 0. Prior to the 2.2 PCI specification, this was the UDF (user defined features) supported bit.
R 0 Does not support UDF
1 Supported user defined features
21 66 MHz capable. Fixed to 1. Indicates the PCI controller is 66 MHz capable.
66M
20 Capabilities list. Fixed to 0. Indicates the PCI controller does not implement the new capabilities list pointer
C configuration register in DWORD 13 of the configuration space.
19–10 Reserved, must be cleared.
9 Fast back-to-back transfer enable. Controls if the PCI controller as master can do fast back-to-back transactions to
F different devices. Initialization software should set this bit if all targets are fast back-to-back capable.
0 Fast back-to-back transactions only allowed to the same device
1 The master is allowed to generate fast back-to-back transactions to different devices
8 SERR enable. Enables the PCI_SERR driver.
S 0 PCI_SERR driver disabled
1 PCI_SERR driver enabled
Note: Address parity errors are reported only if this bit and the PER bit are set.
7 Address and data stepping. Fixed to 0. Indicates the PCI controller never uses address/data stepping. Initialization
ST software should write a 0 to this bit location.
6 Parity error response. Controls the device's response to parity errors.
PER 0 The device sets its parity error status bit (PE, bit 31) in the event of a parity error, but does not assert PCI_PERR
1 When a parity error is detected, the PCI controller asserts PCI_PERR
5 VGA palette snoop enable. Fixed to 0. Indicates that the PCI controller is not VGA compatible. Initialization software
V should write a 0 to this bit location.
4 Memory write and invalidate enable. Enables the
MW 0 Only
MEMORY WRITE
1 PCI controller-as-master may generate the
3 Special cycle monitor or ignore. Determines whether or not to ignore PCI special cycles. Because PCI
SP controller-as-target does not recognize messages delivered via the special cycle operation, a value of 1 must never
be programmed to this register. This bit, however, is programmable.
2 Bus master enable. Indicates if the PCI controller has the ability to serve as a master on the PCI bus. A value of 1
B indicates this ability is enabled. If the PCI controller is a master on the PCI bus, a 1 must be written to this bit during
initialization or the PCI controller does not operate as a PCI master. Configuration software reads this bit.
1 Memory access control. Controls the PCI controller's response to memory space accesses.
M 0 The PCI controller does not recognize memory accesses
1 The PCI controller recognizes memory accesses
0 I/O access control. Fixed to 0. This bit is not implemented because there is no PCI controller I/O type space
IO accessible from the PCI bus. The PCI base address registers are memory address ranges only. Initialization software
must write a 0 to this bit location.
Freescale Semiconductor
Table 22-4. PCISCR Field Descriptions (continued)
MEMORY WRITE AND INVALIDATE
command can be used
MEMORY WRITE AND INVALIDATE
Description
command.
command
PCI Bus Controller
22-9