Freescale Semiconductor MCF54455 Reference Manual page 716

SSI_CCR[DC]
Word Clock
Figure 27-38. SSI Transmit Frame Sync Generator Block Diagram
27.4.2.2 DIV2, PSR and PM Bit Description
The bit clock frequency can be calculated from the SSI serial system clock (SSI_CLOCK), using
Equation 27-1.
You must ensure that the bit-clock frequency is at most one-fifth the internal
bus frequency (f
internal bus frequency. Bits DIV2, PSR, and PM must not be cleared at the
same time.
f
INT_BIT_CLK
From this, the frame clock frequency can be calculated:
For example, if the SSI working clock is 19.2 MHz, in 8-bit word normal mode with DC = 1, PM = 0x4A
(74), PSR = 0, DIV2 = 1, a bit clock rate of 64 kHz is generated. Because the 8-bit word rate equals two,
sampling rate (or frame sync rate) would then be 64/(28) = 4 kHz.
In the next example, SSI_CLOCK is 12 MHz. A 16-bit word network mode with DC = 1, PM = 1, the
PSR = 0, DIV2 = 1, a bit clock rate of 12/[142] = 1.5 MHz is generated. Because the 16-bit word rate
equals two, sampling rate (or frame sync rate) would be 1.5/(216) = 46.875 kHz.
Table 27-26 shows the example of programming PSR and PM bits to generate different bit clock
(SSI_BCLK) frequencies. The SSI_CLKIN signal is used in this example (MISCCR[SSISRC] = 0)
because when operating the processor at the typical 266 MHz frequency, the SSI module is not able to
accurately produce standard bit and sample rates.
Table 27-26. SSI Bit Clock and Frame Rate as a Function of PSR, PM, and DIV2
SSI_CLKIN
freq (MHz)
(SSI_MCLK)
12.288
12.288
Freescale Semiconductor
Frame Frame
TFSL
Rate Sync
Tx Frame Sync Out
Tx
Control
Tx Frame Sync In
). The oversampling clock frequency can go up to
sys/2
SSI serial system clock
=
------------------------------------------------------------------------------------------------------------ -
   
DIV2 + 1 7
f
INT_BIT_CLK
f =
------------------------------------------------------------------ -
FS_CLK  
DC + 1
SSI_CCR
DIV2 PSR PM
0 0 23
0 0 11
TFDIR(1=output)
TFSI
TFDIR(0=input)
TFSI
NOTE
     
PSR + 1 PM + 1 2
     
2 WL + 1
Bit Clk (kHz)
SSI_BCLK
WL DC
3 3 256
3 3 512
Synchronous Serial Interface (SSI)
SSI_FS
Eqn. 27-1
Eqn. 27-2
Frame rate
(kHz)
8
16
27-49