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2
I
C Interface
33.2
Memory Map/Register Definition
The below table lists the configuration registers used in the I
Address
2
0xFC05_8000 I
C Address Register (I2ADR)
2
0xFC05_8004 I
C Frequency Divider Register (I2FDR)
2
0xFC05_8008 I
C Control Register (I2CR)
2
0xFC05_800C I
C Status Register (I2SR)
2
0xFC05_8010 I
C Data I/O Register (I2DR)
2
33.2.1
I
C Address Register (I2ADR)
I2ADR holds the address the I
bus during the address transfer when the module is performing a master transfer.
Address: 0xFC05_8000 (I2ADR)
7
R
W
Reset:
0
Field
7–1
Slave address. Contains the specific slave address to be used by the I
ADR
for an address match on the bus.
0
Reserved, must be cleared.
2
33.2.2
I
C Frequency Divider Register (I2FDR)
The I2FDR, shown in
Figure
bit-rate selection.
Address: 0xFC05_8004 (I2FDR)
7
R
0
W
Reset:
0
33-3
2
Table 33-1. I
C Module Memory Map
Register
2
C responds to when addressed as a slave. It is not the address sent on the
6
5
ADR
0
0
0
2
Figure 33-2. I
C Address Register (I2ADR)
Table 33-2. I2ADR Field Descriptions
33-3, provides a programmable prescaler to configure the I
6
5
0
0
0
0
2
Figure 33-3. I
C Frequency Divider Register (I2FDR)
2
C interface.
Access Reset Value
R/W
R/W
R/W
R/W
R/W
4
3
2
0
0
Description
2
C module. Slave mode is the default I
4
3
2
IC
0
0
Section/Page
0x00
33.2.1/33-3
0x00
33.2.2/33-3
0x00
33.2.3/33-4
0x81
33.2.4/33-5
0x00
33.2.5/33-6
Access: User read/write
1
0
0
0
0
2
C mode
2
C clock for
Access: User read/write
1
0
0
0
Freescale Semiconductor
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