Timing Variations - Freescale Semiconductor MCF54455 Reference Manual

Figure 20-15 illustrates the longword write to a 32-bit device.
Mux'd Bus
Non-Mux'd Bus
FB_CSn, FB_BE/BWEn
20.4.6.4

Timing Variations

The FlexBus module has several features that can change the timing characteristics of a basic read- or
write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch
data.
20.4.6.4.1 Wait States
Wait states can be inserted before each beat of a transfer by programming the CSCRn registers. Wait states
can give the peripheral or memory more time to return read data or sample write data.
Freescale Semiconductor
S0
FB_CLK
FB_AD[31:0]
ADDR[31:0]
FB_A[23:0]
ADDR[31:0]
FB_D[31:0]
FB_R/W
FB_ALE
FB_OE
FB_TA
FB_TSIZ[1:0]
Figure 20-15. Longword-Write Transfer
S1 S2 S3
DATA[31:0]
ADDR[23:0]
DATA[31:0]
00
FlexBus
S0
20-21