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Cache
bus transaction completes, the cache controller can generate the appropriate line-write bus transaction to
write the push buffer contents into memory.
In imprecise mode, the FIFO store buffer can defer pending writes to maximize performance. The store
buffer can support as many as four entries (16 bytes maximum) for this purpose.
Data writes destined for the store buffer cannot stall the core. The store buffer effectively provides a
measure of decoupling between the pipeline's ability to generate writes (one per cycle maximum) and the
external bus's ability to retire those writes. In imprecise mode, writes stall only if the store buffer is full
and a write operation is on the internal bus. The internal write cycle is held, stalling the data execution
pipeline.
If the store buffer is not used (store buffer disabled or cache-inhibited precise mode), external bus cycles
generate directly for each pipeline-write operation. The instruction is held in the pipeline until external bus
transfer termination is received. Therefore, each write is stalled for five cycles, making the minimum write
time equal to six cycles when the store buffer is not used. See
Section 3.1.1.2, "Operand Execution
Pipeline (OEP)."
The data store buffer enable bit, CACR[DESB], controls the enabling of the data-store buffer. The
MOVEC instruction can set and clear this bit. At reset, this bit is cleared and all writes perform in order
(precise mode). ACRn[CM] or CACR[DDCM] generates the mode used when DESB is set. Cacheable
write-through and cache-inhibited imprecise modes use the store buffer.
The store buffer can queue data as much as four bytes wide per entry. Each entry matches the
corresponding bus cycle it generates; therefore, a misaligned longword write to a write-through region
creates two entries if the address is to an odd-word boundary. It creates three entries if the address is to an
odd-byte boundary—one per bus cycle.
6.4.4.2.2
Push and Store Buffer Bus Operation
As soon as the push or store buffer has valid data, the internal bus controller uses the next available external
bus cycle to generate the appropriate write cycles. In the event another cache fill is required (for example,
cache miss to process) during the continued instruction execution by the processor pipeline, the pipeline
stalls until the push and store buffers empty, before generating the required external bus transaction.
Supervisor instructions, the NOP instruction, and exception processing synchronize the processor core and
guarantee the push and store buffers are empty before proceeding. The NOP instruction should be used
only to synchronize the pipeline. The preferred no-op function is the TPF instruction. See the ColdFire
Programmer's Reference Manual for more information on the TPF instruction.
6.4.5
Cache Locking
Ways 0 and 1 of the data cache can lock by setting CACR[DHLCK]; likewise, ways 0 and 1 of the
instruction cache can lock by setting CACR[IHLCK]. If a cache locks, cache lines in ways 0 and 1 are not
subject to deallocation by normal cache operations.
As
Figure 6-8
(B and C) shows, the algorithm for updating the cache and for identifying cache lines for
deallocation does not change. If ways 2 and 3 are entirely invalid, cacheable accesses are first allocated in
way 2. Way 3 is not used until the location in way 2 is occupied.
Freescale Semiconductor
6-17
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