Interrupt Controller Theory Of Operation - Freescale Semiconductor MCF54455 Reference Manual

Interrupt Controller Modules
Field
7–0 Vector number. A read from the SWIACK register returns the vector number associated with the highest priority
VECTOR pending interrupt source. A read from one of the LnIACK registers returns the highest priority unmasked interrupt
source within the level.
A write to any IACK register causes an error termination.
17.3 Functional Description
17.3.1

Interrupt Controller Theory of Operation

To support the interrupt architecture of the 68K/ColdFire programming model, the 64 interrupt sources are
organized as 7 levels, with an arbitrary number of requests programmed to each level. The priority
structure within a single interrupt level depends on the interrupt source number assignments (see
Section 17.2.9.1, "Interrupt
numbered interrupt source. See the below table for an example.
Interrupt Source
The level is fully programmable for all sources. The 3-bit level is defined in the interrupt control register
(ICR0n, ICR1n).
The operation of the interrupt controller can be broadly partitioned into three activities:
• Recognition
• Prioritization
• Vector determination during IACK
17.3.1.1 Interrupt Recognition
The interrupt controller continuously examines the request sources (IPRn) and the interrupt mask register
(IMRn) to determine if there are active requests. This is the recognition phase. The interrupt force register
(INTFRCn) also factors into the generation of an active request.
17.3.1.2 Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level. Next, the appropriate
level masking is performed if this feature is enabled. The level of the active request must be greater than
the current mask level before it is signaled in the processor. The resulting unmasked decoded priority level
is driven out of the interrupt controller. The decoded priority levels from the interrupt controllers are
17-16
Table 17-17. SWIACKn and LxIACKn Field Descriptions
Sources"). The higher numbered interrupt source has priority over the lower
Table 17-18. Example Interrupt Priority Within a Level
ICR[2:0]
40 011
22 011
8 011
2 011
Description
Priority
Highest
Lowest
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