Fifo Alarm Register (Fifo_Alarm) - Freescale Semiconductor MCF54455 Reference Manual

Advanced Technology Attachment (ATA)
23.3.6.3 Interrupt Clear Register (ATA_ICR)
The interrupt clear register clears the FIFO underflow/overflow status bits in the ATA_ISR register.
Address: 0x9000_0030 (ATA_ICR)
7
R
W
Reset —
Field
7 Reserved.
6 FIFO underfow clear. Writing a 1 to this bit clears the corresponding bit in the ATA_ISR. Writing a 0 has no effect.
FUF
5 FIFO overflow clear. Writing a 1 to this bit clears the corresponding bit in the ATA_ISR. Writing a 0 has no effect.
FOF
4–0 Reserved.
23.3.7

FIFO Alarm Register (FIFO_ALARM)

The FIFO alarm register contains threshold to generate the FIFO transmit and receive requests to the DMA
controller:
• If (ATA_CR[FREFILL] == 1 and and FIFO_FILL < FIFO_ALARM)
then request is sent to the DMA controller to refill the FIFO.
If (ATA_CR[FEMPTY] == 1 and and FIFO_FILL  FIFO_ALARM)
•
then request is sent to the DMA controller to empty the FIFO.
Address: 0x9000_0034 (FIFO_ALARM)
7
R
W
Reset 0
23.3.8 Drive Registers
Some drive registers are addressable, but are not present in ATA interface module.
list of these registers. If a read or write access is made to one of these registers, read or write maps to a PIO
read or write cycle on the ATA bus, and the corresponding register in the device attached to the ATA bus
23-12
6 5
FUF FOF
— —
Figure 23-9. ATA_ICR Register
Table 23-7. ATA_ICR Field Description
6 5
0 0
Figure 23-10. FIFO_Alarm Register
4 3 2
— — —
Description
4 3 2
FIFO_ALARM
0 0 0
Access: User write-only
1 0
— —
Access: User read/write
1 0
0 0
Table 23-2 provides a
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