Memory Map/Register Definition - Freescale Semiconductor MCF54455 Reference Manual

— Provides control and maintenance of TLBs
— Provides fault status and recovery information functions
• Separate, 32-entry, fully associative instruction and data TLBs (Harvard TLBs)
— Resides in the processor local bus-controller
— Operates in parallel with internal memory
— Suffers no performance penalty on TLB hits
— Supports 4- and 8-Kbyte, and 1- and 16-Mbyte page sizes concurrently
— Contains register-based TLB entries
• Core extensions:
— User stack pointer
— All access error exceptions are precise and recoverable
• Harvard TLB provides 97% of baseline performance on large embedded applications without
MMU support
4.2

Memory Map/Register Definition

Access to the MMU memory-mapped region is controlled by MMUBAR, a 32-bit supervisor control
register at 0x008 accessed using MOVEC or the serial BDM debug port. The ColdFire Programmers
Reference Manual describes the MOVEC instruction.
MMUBAR holds the base address for the 64-Kbyte MMU memory map
map area is not visible unless the MMUBAR is valid and must be referenced aligned. A large map portion
is reserved for future use.
Address
Rc[11:0] = ASID—Address Space ID
1
0x003
Rc[11:0] = MMUBAR—MMU Base Address Register
1
0x008
MMUBAR MMUCR—MMU control register
+ 0x0000
MMUBAR MMUOR—MMU operation register
+ 0x0004
MMUBAR MMUSR—MMU status register
+ 0x0008
MMUBAR MMUAR—MMU fault, test, or TLB address register
+ 0x0010
MMUBAR MMUTR—MMU read/write TLB tag register
+ 0x0014
Freescale Semiconductor
Table 4-1. MMU Memory Map
Register
Memory Management Unit (MMU)
(Table 4-1). The MMU memory
Width Access Reset Value
8 R/W 0x00
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
Section/Page
4.2.1/4-4
4.2.2/4-4
4.2.3/4-5
4.2.4/4-6
4.2.5/4-7
4.2.6/4-8
4.2.7/4-8
4-3