Freescale Semiconductor MCF54455 Reference Manual page 572

PCI inbound address translation allows address translation to any space in local memory (4 Gbytes of
address space). The target base address translation registers, PCITBATRn, specify the location of the
inbound memory window. These registers are described in
Address translation occurs for all enabled inbound transactions. If the PCITBATRn[EN] bit is cleared, the
PCI controller aborts all PCI memory transactions to that base address window.
The PCI configuring master can program the PCIBARn registers to
overlapping PCI addresses. The default address translation value is
PCITBATR5 in that case. It is not recommended to program overlapping
PCIBAR space or overlapping PCITBATRs. An overlap of the PCITBATRn
registers can cause data write-over of lower PCIBAR data.
The initiator window base address registers, PCIIWnBTAR, decode internal bus addresses for PCI bus
transactions. The base address and base address mask values define the upper byte of address to decode.
The internal bus address space dedicated to PCI transactions can be mapped to three 16-Mbyte or larger
address spaces in the device. Initiator windows can be programmed to overlap, though not recommended.
Priority for the windows is 0, 1, 2. Initiator window 0 has priority over all others and window 1 has priority
over window 2.
In normal operation, software must not program either target address window translation register to
address initiator window space. In that event, a PCI controller-as-target transaction propagates through the
device's internal bus and requests PCI bus access as the PCI initiator. The PCI arbiter could see the PCI
bus as busy (target read transaction in progress) and only a time-out frees the PCI bus.
ColdFire Processor Space
0
Inbound
Translation
Base Address 0
1G
Initiator
Windows
2G
Inbound
Translation
Base Address5
3G
4G
Freescale Semiconductor
NOTE
PCITBATR0
Register Space Address
Translation
Recommended
PCI Space
PCITBATR5
Address
SDRAM Space
Translation
Figure 22-44. Inbound Address Map
Section 22.4.2, "Configuration Interface."
PCI Space (Memory View)
0
System Memory
1G
Not
PCI Controller Memory
2G
PCI Controller Memory
3G
4G
PCI Bus Controller
PCI Controller
BAR5
PCI Controller
BAR0
22-55