Delay Settings - Freescale Semiconductor MCF54455 Reference Manual

31.5.4

Delay Settings

Table 31-22 shows the values for the delay after transfer (t
generated based on the prescaler values and the scaler values set in the DSPI_CTARn registers. The values
calculated assume a 100 MHz system frequency.
Freescale Semiconductor
Table 31-21. Baud Rate Values
Baud Rate Divider Prescaler Values
(DSPI_CTARn[PBR])
2
25.0MHz 16.7MHz
2
12.5MHz 8.33MHz
4
8.33MHz 5.56MHz
6
6.25MHz 4.17MHz
8
3.12MHz 2.08MHz
16
1.56MHz 1.04MHz
32
781kHz 521kHz
64
391kHz 260kHz
128
195kHz 130kHz
256
97.7kHz 65.1kHz
512
48.8kHz 32.6kHz
1024
24.4kHz 16.3kHz
2048
12.2kHz 8.14kHz
4096
6.10kHz 4.07kHz
8192
3.05kHz 2.04kHz
16384
1.53kHz 1.02kHz
32768
DMA Serial Peripheral Interface (DSPI)
3 5
10.0MHz 7.14MHz
5.00MHz 3.57MHz
3.33MHz 2.38MHz
2.50MHz 1.79MHz
1.25MHz 893kHz
625kHz 446kHz
312kHz 223kHz
156kHz 112kHz
78.1kHz 55.8kHz
39.1kHz 27.9kHz
19.5kHz 14.0kHz
9.77kHz 6.98kHz
4.88kHz 3.49kHz
2.44kHz 1.74kHz
1.22kHz 872Hz
610Hz 436Hz
) and CS to SCK delay (t
DT
7
) that can be
CSC
31-39