Freescale Semiconductor MCF54455 Reference Manual page 250

Address: 0xFC0B_01B8 (EPSR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–20 Reserved, must be cleared.
19–16 Endpoint transmit buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. The
ETBR hardware sets this bit in response to receiving a command from a corresponding bit in the EPPRIME register. A
constant delay exists between setting a bit in the EPPRIME register and endpoint indicating ready. This delay time
varies based upon the current USB traffic and the number of bits set in the EPPRIME register. USB reset, USB DMA
system, or EPFLUSH register clears the buffer ready. ETBR[3] (bit 19) corresponds to endpoint 3.
Note: Hardware momentarily clears these bits during hardware endpoint re-priming operations when a dTD is
retired, and the dQH is updated.
15–4 Reserved, must be cleared.
3–0 Endpoint receive buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. The
ERBR hardware sets this bit in response to receiving a command from a corresponding bit in the EPPRIME register. A
constant delay exists between setting a bit in the EPPRIME register and endpoint indicating ready. This delay time
varies based upon the current USB traffic and the number of bits set in the EPPRIME register. USB reset, USB DMA
system, or EPFLUSH register clears the buffer ready. ERBR[3] (bit 19) corresponds to endpoint 3.
Note: Hardware momentarily clears these bits during hardware endpoint re-priming operations when a dTD is
retired, and the dQH is updated.
10.3.4.21 Endpoint Complete Register (EPCOMPLETE)
This register is not defined in the EHCI specification. This register is used only in device mode.
Address: 0xFC0B_01BC (EPCOMPLETE)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 10-37. Endpoint Complete Register (EPCOMPLETE)
Field
31–20 Reserved, must be cleared.
19–16 Endpoint transmit complete event. Each bit indicates a transmit event (IN/INTERRUPT) occurs and software must
ETCE read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the
transfer descriptor, this bit is set simultaneously with the USBINT. Writing a 1 clears the corresponding bit in this
register. ETCE[3] (bit 19) corresponds to endpoint 3.
Freescale Semiconductor
ETBR
Figure 10-36. Endpoint Status Register (EPSR)
Table 10-39. EPSR Field Descriptions
Description
ETCE
w1c
Table 10-40. EPCOMPLETE Field Descriptions
Description
Universal Serial Bus Interface – On-The-Go Module
9 8 7
0 0 0 0 0 0 0 0 0 0 0 0
9 8 7
0 0 0 0 0 0 0 0 0 0 0 0
Access: User read-only
6 5 4 3 2 1 0
ERBR
Access: User read/write
6 5 4 3 2 1 0
ERCE
w1c
10-43