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Freescale Semiconductor

MCF54455 Reference Manual

by: Microcontroller Solutions Group

This is the MCF54455 Reference Manual set consisting of the following files:

•

MCF54455 Reference Manual Errata, Rev 1

•

MCF54455 Reference Manual, Rev 6

MCF54455RM

Rev. 6.1, 03/2012

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Summary of Contents for Freescale Semiconductor MCF54455

Page 1 Freescale Semiconductor MCF54455RM Rev. 6.1, 03/2012 MCF54455 Reference Manual by: Microcontroller Solutions Group This is the MCF54455 Reference Manual set consisting of the following files: • MCF54455 Reference Manual Errata, Rev 1 • MCF54455 Reference Manual, Rev 6 © Freescale Semiconductor, Inc., 2012. All rights reserved.
Page 2 MC54455RM. For convenience, the addenda items are grouped by revision. Please check our website at http://www.freescale.com for the latest updates. The current available version of the MCF54455 Reference Manual is Revision 6. © Freescale Semiconductor, Inc., 2011. All rights reserved.
Page 3: Revision History
Errata for Revision 6 Errata for Revision 6 Table 1. MCF54455 Reference Manual Rev 6 Errata Location Description Section 16.2, “External Signal Add pin N7 to the VSS pin list for the 360 TEPBGA. Description”/Table 16-2/Page 16-11 Revision History Table 2 provides a revision history for this document.
Page 4 THIS PAGE IS INTENTIONALLY LEFT BLANK MCF54455 Reference Manual Errata, Rev. 1 Freescale Semiconductor...
Page 5: Home Page
0120 191014 or +81 3 5437 9125 or other applications intended to support or sustain life, or for any other support.japan@freescale.com application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer Asia/Pacific:...
Page 6 MCF54455 Reference Manual Devices Supported: MCF54450 MCF54451 MCF54452 MCF54453 MCF54454 MCF54455 Document Number: MCF54455RM Rev. 6 5/2011...
Page 7 Freescale Semiconductor product could Asia/Pacific: create a situation where personal injury or death may occur. Should Buyer Freescale Semiconductor China Ltd.
Page 8: Table Of Contents
1.6.21 DMA Serial Peripheral Interface (DSPI) ......1-8 1.6.22 Universal Asynchronous Receiver Transmitters (UARTs) ....1-9 Freescale Semiconductor...
Page 9 Overview ............3-2 Freescale Semiconductor...
Page 10 MMU Instructions ..........4-23 Freescale Semiconductor...
Page 11 7.1 Introduction ............7-1 Freescale Semiconductor...
Page 12 Peripheral Behavior in Low-Power Modes ......9-9 9.3.5 Summary of Peripheral State During Low-power Modes ....9-14 Freescale Semiconductor...
Page 13 11.3.5 Clock-Divider Register (CDR) ........11-11 11.3.6 USB On-the-Go Controller Status Register (UOCSR) ....11-11 viii Freescale Semiconductor...
Page 14 14.1 Introduction ............14-1 Freescale Semiconductor...
Page 15 16.3.3 Port Pin Data/Set Data Registers (PPDSDR_x) ..... . 16-20 16.3.4 Port Clear Output Data Registers (PCLRR_x) ..... . . 16-23 Freescale Semiconductor...
Page 16 18.4.5 Edge Port Pin Data Register (EPPDR) ......18-5 Freescale Semiconductor...
Page 17 19.6.7 Dynamic Programming ......... 19-37 Chapter 20 Freescale Semiconductor...
Page 18 21.4 Memory Map/Register Definition ......... 21-9 Freescale Semiconductor...
Page 19 22.3.2 General Control/Status Registers ....... . . 22-14 Freescale Semiconductor...
Page 20 24.1 Introduction ............24-2 Freescale Semiconductor...
Page 21 26.4 Memory Map/Register Definition ......... 26-6 Freescale Semiconductor...
Page 22 26.5.16 RMII Echo ........... 26-47 26.5.17 Ethernet Error-Managing Procedure ....... 26-47 Freescale Semiconductor xvii...
Page 23 27.5 Initialization/Application Information ........27-53 xviii Freescale Semiconductor...
Page 24 29.3.2 Free-Running Timer Operation ........29-6 Freescale Semiconductor...
Page 25 31.3.1 DSPI Module Configuration Register (DSPI_MCR) ....31-5 31.3.2 DSPI Transfer Count Register (DSPI_TCR) ......31-8 Freescale Semiconductor...
Page 26 32.3.12 UART Input Port Register (UIPn) ....... . . 32-15 32.3.13 UART Output Port Command Registers (UOP1n/UOP0n) ....32-16 Freescale Semiconductor...
Page 27 33.4.7 Arbitration Lost ..........33-14 Chapter 34 Debug Module xxii Freescale Semiconductor...
Page 28 35.3.3 Bypass Register ..........35-5 Freescale Semiconductor...
Page 29 A.4 Changes Between Rev. 5 and Rev. 6 ........1-5 xxiv Freescale Semiconductor...
Page 30: About This Book
Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield • Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David A. Patterson. • Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A. Patterson and John L. Hennessy. Freescale Semiconductor...
Page 31: Coldfire Documentation
• Application notes — These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors. Additional literature is published as new processors become available. For a current list of ColdFire documentation, refer to http://www.freescale.com/coldfire.
Page 32: Register Figure Conventions
Indicates a read-only bit field in a memory-mapped register. Indicates a write-only bit field in a memory-mapped register. W FIELDNAME R FIELDNAME Write 1 to clear: indicates that writing a 1 to this bit field clears it. Indicates a self-clearing bit. W FIELDNAME Freescale Semiconductor xxvii...
Page 33 Freescale Semiconductor...
Page 34: Overview
The following table compares the various device derivatives available within the MCF5445x family. Table 1-1. MCF5445x Family Configurations Module MCF54450 MCF54451 MCF54452 MCF54453 MCF54454 MCF54455 ColdFire Version 4 Core with EMAC • • • • • • (Enhanced Multiply-Accumulate Unit)
Page 35 Overview Table 1-1. MCF5445x Family Configurations (continued) Module MCF54450 MCF54451 MCF54452 MCF54453 MCF54454 MCF54455 Fast Ethernet Controller (FEC) UARTs • • • • • • DSPI • • • • • • Real Time Clock • • • • •...
Page 36: Block Diagram
Overview Block Diagram Figure 1-1 shows a top-level block diagram of the MCF54455 superset device. MCF54455 JTAG Oscillator Version 4 ColdFire Core Instruction Cache Data EMAC 2 FECs USB OTG Cache Hardware Divide eDMA Serial Boot SRAM Crossbar Switch (XBS)
Page 37: Operating Parameters
DMA supported serial peripheral interface (DSPI) • 3 UARTs • C bus interface Module-by-Module Feature List The following is a brief summary of the functional blocks in the MCF54455 superset device. For more details refer to the MCF54455 ColdFire Microprocessor Reference Manual (MCF54455RM). Freescale Semiconductor...
Page 38: Version 4 Coldfire Variable-Length Risc Processor
Software controlled disable of external clock input for low power consumption 1.6.5 Chip Configuration Module (CCM) • System configuration during reset • Bus monitor, abort monitor • Configurable output pad drive strength control • Unique part identification and part revision numbers • Serial boot capability Freescale Semiconductor...
Page 39: Reset Controller
16-byte critical word first burst transfer • Up to 14 lines of row address, up to 11 column address lines (16-bit bus), 2 bits of bank address, and two pinned-out chip selects. The maximum row bits plus column bits equals 25. Freescale Semiconductor...
Page 40: Flexbus (External Interface)
FIFO receive alarm, FIFO transmit alarm and FIFO end of transmission alarm to DMA unit • Zero-wait cycles transfer between DMA bus and FIFO allows fast FIFO reading/writing 1.6.15 Fast Ethernet Media Access Controller (FEC MAC) • 10/100 BaseT/TX capability, half duplex or full duplex Freescale Semiconductor...
Page 41: Random Number Generator (Rng)
Input capture and reference compare modes 1.6.21 DMA Serial Peripheral Interface (DSPI) • Full-duplex, three-wire synchronous transfer • Up to five chip selects available • Master and slave modes with programmable master bit-rates • Up to 16 pre-programmed transfers Freescale Semiconductor...
Page 42: Universal Asynchronous Receiver Transmitters (Uarts)
Support for major and minor nested counters with one request and one interrupt per channel • Support for channel-to-channel linking and scatter/gather for continuous transfers with fixed priority and round-robin channel arbitration • External request pins for up to 2 channels Freescale Semiconductor...
Page 43: General Purpose I/O Interface
General Purpose I/O interface • Up to 93 bits of GPIO for the MCF54450 and MCF54451 • Up to 132 bits of GPIO for the MCF54452, MCF54453, MCF54454, and MCF54455 • Bit manipulation supported via set/clear functions • Various unused peripheral pins may be used as GPIO 1.6.28...
Page 44: Internal Peripheral Space
Real-Time Clock 0xFC04_0000 SCM (CWT and Core Fault Registers) 0xFC04_4000 eDMA Controller 0xFC04_8000 Interrupt Controller 0 0xFC04_C000 Interrupt Controller 1 0xFC05_4000 Interrupt Controller IACK 0xFC05_8000 0xFC05_C000 DSPI 0xFC06_0000 UART0 0xFC06_4000 UART1 0xFC06_8000 UART2 0xFC07_0000 DMA Timer 0 Freescale Semiconductor 1-11...
Page 45: Documentation
PCI Arbiter 0xFC0B_0000 USB On-the-Go 0xFC0B_4000 0xFC0B_8000 SDRAM Controller 0xFC0B_C000 0xFC0C_4000 Documentation Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire. 1-12 Freescale Semiconductor...
Page 46: Signal Descriptions
Most pins that are muxed with GPIO default to their GPIO functionality. See Table 2-1 for a list of the exceptions. Table 2-1. Special-Case Default Signal Functionality 256 MAPBGA 360 TEPBGA FB_AD[31:0] FB_AD[31:0] except when serial boot selects 0-bit boot port size. FB_BE/BWE[3:0] FB_BE/BWE[3:0] FB_CS[3:1] FB_CS[3:1] Freescale Semiconductor...
Page 47 ATA_RESET GPIO ATA reset Table 2-2. MCF5445x Signal Information and Muxing MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA Reset RESET — — — EVDD RSTOUT — — — — EVDD...
Page 48 Signal Descriptions Table 2-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA FB_CLK — — — — EVDD FB_CS[3:1] PCS[3:1] — — — EVDD C2, D4, C3...
Page 49 Signal Descriptions Table 2-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA PCI_RST — — — — EVDD — PCI_SERR — — — — EVDD —...
Page 50 Signal Descriptions Table 2-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA FEC0_COL PFEC0H4 — ULPI_DATA7 — EVDD FEC0_CRS PFEC0H0 — ULPI_DATA6 — EVDD FEC0_RXCLK PFEC0H3 —...
Page 51 Signal Descriptions Table 2-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA FEC1_TXD1 PFEC1L5 FEC1_RMII_TXD1 ATA_DATA10 — EVDD — AA19 FEC1_TXD0 PFEC1H5 FEC1_RMII_TXD0 ATA_DATA9 —...
Page 52 Signal Descriptions Table 2-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA I2C_SDA PFECI2C0 — U2RXD EVDD DACK1 PDMA3 — ULPI_DIR — EVDD DREQ1 PDMA2 —...
Page 53 Table 2-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA BDM/JTAG PSTDDATA[7:0] — — — — EVDD E2, D1, F4, E3, AA6, AB6, AB5, D2, C1, E4, D3...
Page 54: Signal Primary Functions
RSTOUT is asserted at least 512 internal system bus clock cycles (256 FB_CLK cycles) in response to any internal or external reset. (The exact time depends on how long it takes for the PLL to lock and/or the serial boot sequence to complete.) Freescale Semiconductor...
Page 55: Pll And Clock Signals
2.3.3 Mode Selection Table 2-5. Mode Selection Signals Signal Name Abbreviation Function Boot mode BOOTMOD[1:0] Indicates the device’s boot mode and chip configuration at reset. See Chapter 11, “Chip Configuration Module (CCM),” for the signal encodings. 2-10 Freescale Semiconductor...
Page 56: Flexbus Signals
FB_ALE is asserted for one bus clock cycle. In multiplexed mode, ALE is used externally as an address latch enable to capture the address phase of the bus transfer. Chip Selects FB_CS[3:0] Select external devices for external bus transactions. Freescale Semiconductor 2-11...
Page 57: Sdram Controller Signals
Reference voltage for differential I/O pad cells. Should be half the voltage of the memory used in the system. For example, 2.5 V DDR results in an SD_VREF of 1.25 V. See the device’s datasheet for the voltages and tolerances for the various memory modes. 2-12 Freescale Semiconductor...
Page 58: Pci Controller Signals
Indicates that the currently addressed target wishes to stop the current transaction. PCI Target Ready PCI_TRDY Indicates currently addressed target is ready to complete the current data phase. PCI Interrupt A PCI_INTA This output is the PCI interrupt A signal. Freescale Semiconductor 2-13...
Page 59: Serial Boot Facility Signals
Asserted upon collision detection and remains asserted while collision persists. This signal is not defined for full-duplex mode. Carrier Receive Sense FECn_CRS When asserted, indicates transmit or receive medium is not idle. Applies to MII mode operation. 2-14 Freescale Semiconductor...
Page 60: I2C I/O Signals
C module when the bus is in master mode, or it becomes the clock input when the I C is in slave mode. Serial Data I2C_SDA Open-drain signal serving as the data input/output for the I interface. Freescale Semiconductor 2-15...
Page 61: Ata Controller Signals
STOP, signalling when the host wants to terminate an ultra DMA transfer. ATA Interrupt Request ATA_INTRQ This input signal is the ATA bus interrupt request. It is asserted by the device when it wants to interrupt. 2-16 Freescale Semiconductor...
Page 62: Dma Serial Peripheral Interface (Dspi) Signals
SSI_FS during the rising edge of SSI_BCLK. Serial Receive Data SSI_RXD Receives data into the receive data shift register Serial Transmit Data SSI_TXD Transmits data from the serial transmit shift register. Freescale Semiconductor 2-17...
Page 63: Universal Serial Bus (Usb) Signals
UART clock is stopped for power-down mode, any transition on this pin restarts it. Clear-to-Send UnCTS Indicates UART modules can begin data transmission Request-to-Send UnRTS Automatic request-to-send outputs from UART modules. They may also be asserted and negated as a function of the received FIFO level. 2-18 Freescale Semiconductor...
Page 64: Dma Timer Signals
Processor Status Clock PSTCLK Used by the development system to know when to sample DDATA and PST signals. Processor Status/ PSTDDATA[7:0] Display captured processor status and captured address/data values. Debug Data These outputs change on the negative edge of PSTCLK. Freescale Semiconductor 2-19...
Page 65: Test Signals
Reserved for factory testing only and in normal modes of operation should be connected to VSS to prevent unintentional activation of test functions. PLL Test PLL_TEST Reserved for factory testing only and should be treated as a no-connect (NC). 2-20 Freescale Semiconductor...
Page 66: Power And Ground Pins
These pins are the negative supply (ground) for the device. — External Boot Mode After reset the address bus, data bus, FlexBus control signals, and SDRAM control signals default to their bus functionalities. All other signals default to GPIO inputs (if applicable). Freescale Semiconductor 2-21...
Page 67 Freescale Semiconductor...
Page 68: Coldfire Core
This chapter also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. 3.1.1 Overview As with all ColdFire cores, the V4 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer. Freescale Semiconductor...
Page 69 Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions. Freescale Semiconductor...
Page 70 (strongly or weakly; taken or not-taken) for each entry. The branch cache also provides the association between instruction addresses and the corresponding target address. In the event of a branch cache hit, if the branch is predicted as taken, the branch cache sources the target address Freescale Semiconductor...
Page 71: Memory Map/Register Description
The programming model is selected based on the processor privilege level (user mode or supervisor mode) as defined by the S bit of the status register (SR). Table 3-1 lists the processor registers. The user-programming model consists of the following registers: • 16 general-purpose 32-bit registers (D0–D7, A0–A7) • 32-bit program counter (PC) Freescale Semiconductor...
Page 72 Load: 0x082–7 Data Register 2–7 (D2–D7) Undefined 3.2.1/3-7 Store: 0x182–7 Load: 0x088–8E Address Register 0–6 (A0–A6) Undefined 3.2.2/3-8 Store: 0x188–8E Load: 0x08F Supervisor/User A7 Stack Pointer (A7) Undefined 3.2.3/3-8 Store: 0x18F 0x804 MAC Status Register (MACSR) 0x0000_0000 5.2.1/5-4 Freescale Semiconductor...
Page 73: Data Registers (D0-D7)
D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they can also be used as index registers. NOTE Registers D0 and D1 contain hardware configuration details after reset. See Section 3.3.4.15, “Reset Exception” for more details. Freescale Semiconductor...
Page 74: Address Registers (A0-A6)
(A7), originally defined for ColdFire ISA_A, is available. EUSP is cleared at reset. To support dual stack pointers, the following two supervisor instructions are included in the ColdFire instruction set architecture to load/store the USP: move.l Ay,USP;move to USP Freescale Semiconductor...
Page 75: Condition Code Register (Ccr)
Reserved, must be cleared. Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified result. Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared. Freescale Semiconductor...
Page 76: Program Counter (Pc)
VBR. The lower 20 bits of the VBR are not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on a 1 MB boundary. Freescale Semiconductor 3-10...
Page 77: Status Register (Sr)
Reserved, must be cleared. Supervisor/user state. 0 User mode 1 Supervisor mode Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or move to SR instructions. Reserved, must be cleared. 3-11 Freescale Semiconductor...
Page 78: Memory Base Address Register (Rambar)
The following figure presents the top-level spatial block diagram of the Version 4 ColdFire operand execution pipeline, where the major hardware structures associated with each pipeline stage are clearly visible. Freescale Semiconductor 3-12...
Page 79 ColdFire Core Extended Extension 2 Opword Opword Extension 1 Register File Base Index Operand Memory EMAC Figure 3-9. Version 4 ColdFire Processor Operand Execution Pipeline Diagram 3-13 Freescale Semiconductor...
Page 80: Instruction Set Architecture (Isa_C)
Zero-fills source operand and moves it to destination register. SATS.L Performs saturation operation for signed arithmetic and updates destination register, depending on CCR[V] and bit 31 of the register. TAS.B Performs indivisible read-modify-write cycle to test and set addressed memory byte. Bcc.L Branch conditionally, longword Freescale Semiconductor 3-14...
Page 81: Exception Processing Overview
4. The processor calculates the address of the first instruction of the exception handler. By definition, the exception vector table is aligned on a 1 MB boundary. This instruction address is generated by fetching an exception vector from the table located at the address defined in the vector base register. 3-15 Freescale Semiconductor...
Page 82 62–63 0x0F8–0x0FC — Reserved 64–255 0x100–0x3FC Next Device-specific interrupts Fault refers to the PC of the instruction that caused the exception. Next refers to the PC of the instruction that follows the instruction that caused the fault. Freescale Semiconductor 3-16...
Page 83: Exception Stack Frame Definition
0101 TLB miss on opword of instruction fetch 0110 TLB miss on extension word of instruction fetch 0111 IFP access error while executing in emulator mode 1000 Error on operand write 1001 Attempted write to write-protected space 3-17 Freescale Semiconductor...
Page 84: Processor Exceptions
TLB miss or another type of access error, new FS encodings (described in Table 3-7) signal TLB misses on instruction fetch, instruction extension fetch, and data read and writes. Freescale Semiconductor 3-18...
Page 85: Address Error Exception
Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR) Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ) Logical OR (OR) Subtract (SUB), Subtract Extended (SUBX) EMAC, Move 3-bit Quick (MOV3Q) Compare (CMP), Exclusive-OR (EOR) 3-19 Freescale Semiconductor...
Page 86 3. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in the previous step. Freescale Semiconductor 3-20...
Page 87 ColdFire processor. If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address 3-21 Freescale Semiconductor...
Page 88 After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at address 0x0000_0000 is loaded into the supervisor stack pointer and the second longword at address Freescale Semiconductor 3-22...
Page 89 EMAC present. This bit signals if the optional enhanced multiply-accumulate (EMAC) execution engine is present in EMAC processor core. 0 EMAC execute engine not present in core. 1 EMAC execute engine is present in core. (This is the value used for this device.) 3-23 Freescale Semiconductor...
Page 90 Information loaded into D1 defines the local memory hardware configuration as shown in the figure below. BDM: Load: 0x081 (D1) Access: User read-only BDM read-only Store: 0x181 (D1) CLSZ ICAS ICSZ Reset MBSZ CPES DCAS DCSZ SRAMSZ Reset Figure 3-13. D1 Hardware Configuration Info Freescale Semiconductor 3-24...
Page 91 0000 No data cache 0001 512 bytes 0010 1 KB 0011 2 KB 0100 4 KB 0101 8 KB 0110 16 KB (This is the value used for this device) 0111 32 KB Else Reserved for future use 3-25 Freescale Semiconductor...
Page 92: Precise Faults
This instruction takes one cycle to read the source operand (Ay) and one to write the data into Ax. Source and destination address pointers are updated as part of execution. Table 3-11 lists the operations performed in execute stage (EX). Freescale Semiconductor 3-26...
Page 93: Instruction Execution Timing
R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation performing a read-modify-write function is denoted as (1/1). This section includes the assumptions concerning the timing values and the execution time details. 3-27 Freescale Semiconductor...
Page 94 Size Operations C(R/W) 01 or 11 Word Byte, Byte 2(1/0) if read 1(0/1) if write 01 or 11 Long Byte, Word, 3(2/0) if read Byte 2(0/2) if write Long Word, Word 2(1/0) if read 1(0/1) if write Freescale Semiconductor 3-28...
Page 95: Move Instruction Execution Times
1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) (Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (Ay)+ 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) -(Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (d16,Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — — 3-29 Freescale Semiconductor...
Page 96 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) — TST.B <ea> 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) TST.W <ea> 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) TST.L <ea> 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) Freescale Semiconductor 3-30...
Page 97 1(0/0) — — — — — — — <ea>,Ax — 1(0/0) — — 1(0/0) 2(0/0) 1(0/0) — LSL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0) LSR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0) 3-31 Freescale Semiconductor...
Page 98: Miscellaneous Instruction Execution Times
— — — — — — MOVEM.L <ea>, and — n(n/0) — — n(n/0) — — — list MOVEM.L — n(0/n) — — n(0/n) — — — list,<ea> <ea>,Dx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) Freescale Semiconductor 3-32...
Page 99 — — — — — 7(0/0) MOVE.L <ea>y,Raccext01 1(0/0) — — — — — — 1(0/0) MOVE.L <ea>y,Raccext23 1(0/0) — — — — — — 1(0/0) MOVE.L Raccx, <ea>x 1(0/0) — — — — — — — 3-33 Freescale Semiconductor...
Page 100 Branch Instruction Execution Times Table 3-19. General Branch Instruction Execution Times Effective Address Opcode <EA> (d16,An) (d8,An,Xi*SF) (An) (An)+ -(An) xxx.wl #xxx (d16,PC) (d8,PC,Xi*SF) — — — — 1(0/1) — — — — — — — 1(0/1) — — — Freescale Semiconductor 3-34...
Page 101 3. For the RTS opcode, the timing depends on the prediction results of the hardware return stack: a) If predicted correctly, 2(1/0). b) If mispredicted, 9(1/0). c) If not predicted, 8(1/0). 3-35 Freescale Semiconductor...
Page 102: Memory Management Unit (Mmu)
MMU control registers and loading TLBs. With software support, the MMU provides demand-paged, virtual addressing. 4.1.1 Block Diagram Figure 4-1 shows the placement of the MMU/TLB hardware. It follows a traditional model closely coupled to the processor local-memory controllers. Freescale Semiconductor...
Page 103: Features
Module Debug DDATA DSCLK DSI PSTDDATA PSTCLK Figure 4-1. CF4 Processor Core Block with MMU 4.1.2 Features The MMU has the following features: • MMU memory-mapped control, status, and fault registers — Supports a flexible, software-defined virtual environment Freescale Semiconductor...
Page 104: Memory Map/Register Definition
MMUBAR MMUOR—MMU operation register 0x0000_0000 4.2.4/4-6 + 0x0004 MMUBAR MMUSR—MMU status register 0x0000_0000 4.2.5/4-7 + 0x0008 MMUBAR MMUAR—MMU fault, test, or TLB address register 0x0000_0000 4.2.6/4-8 + 0x0010 MMUBAR MMUTR—MMU read/write TLB tag register 0x0000_0000 4.2.7/4-8 + 0x0014 Freescale Semiconductor...
Page 105: Address Space Id (Asid)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-3. MMU Base Address Register (MMUBAR) Freescale Semiconductor...
Page 106: Mmu Control Register (Mmucr)
SG is set and ASID does not equal 0. All users and the supervisor share an entry if SG is set and ASID equals 0 Virtual mode enable. 0 Virtual mode is disabled 1 Virtual mode is enabled Freescale Semiconductor...
Page 107: Mmu Operation Register (Mmuor)
ITLB operation. Used by TLB search and access operations that use the TLB allocation address. ITLB 0 MMU uses DTLB to search or update allocation address 1 MMU uses ITLB for of the allocation address searches and updates Freescale Semiconductor...
Page 108: Mmu Status Register (Mmusr)
Write-access fault. Indicates if the last data fault was a data-write access that hit in a TLB entry without its write bit set. 0 Last data access fault did not have a write protect fault 1 Last data access fault had a write protect fault Reserved, must be cleared. Freescale Semiconductor...
Page 109: Mmu Fault, Test, Or Tlb Address Register (Mmuar)
MMUTR and MMUDR contents into the TLB tag and data entries defined by the allocation address or MMUAR. The MMUTR register contains the virtual address tag, the address space ID (ASID), a shared page indicator, and the valid bit. Freescale Semiconductor...
Page 110: Mmu Read/Write Data Entry Register (Mmudr)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-9. MMU Read/Write TLB Data Register (MMUDR) Freescale Semiconductor...
Page 111: Functional Description
The ColdFire MMU provides a virtual address, demand-paged memory architecture. The MMU supports hardware address translation acceleration using software-managed TLBs. It enforces permission checking on a per-memory request basis, and has control, status, and fault registers for MMU operation. 4-10 Freescale Semiconductor...
Page 112: Virtual Memory Management Architecture
ACR address improvements, supervisor protection, and debugging in a virtual environment. 4.3.1.2.1 Precise Faults The MMU architecture performs virtual-to-physical address translation and permission checking in the core. To support demand-paging, the core design provides a precise, recoverable fault for all processor local bus references. Freescale Semiconductor 4-11...
Page 113 Software handles these problems by forcing the virtual address to be equal to the physical address for those bits addressing the cache, but above the in-page address of the smallest active page size. The number of these bits depends on cache and page sizes. 4-12 Freescale Semiconductor...
Page 114 The MMU base-address register (MMUBAR) is added for ColdFire virtual mode. Like other control registers, it can be accessed from the debug module or written using the privileged MOVEC instruction. Section 4.2.2, “MMU Base Address Register (MMUBAR).” Freescale Semiconductor 4-13...
Page 115: Acr Address Improvements
The revised hit determination becomes: ACRx_Hit = 0; if (ACRn[10] == 1) if ((address[31–24] == ACRn[31–24])) && ((address[23–20] and ~ACRn[19–16]) == (ACRn[23–20] and ~ACRn[19–16]))) ACRx_Hit = 1; else if (address[31–24] and ~ACRn[23–16]) == (ACRn[31–24] and ~ACRn[23–16])) ACRx_Hit = 1; 4-14 Freescale Semiconductor...
Page 116: Debugging In A Virtual Environment
Given the PC address defined in the exception stack frame, the processor reestablishes program execution by transferring control to the given location as part of the RTE (return from exception) instruction. For a detailed description, see Section 3.3.4.16, “Precise Faults.” Freescale Semiconductor 4-15...
Page 117: Access Error Stack Frame Additions
IFP access error while executing in emulator mode (New for MMU) 1000 Error on data write 1001 Attempted write of protected space 1010 TLB miss on data write (New for MMU) 1011 Reserved 1100 Error on data read 4-16 Freescale Semiconductor...
Page 118: Effective Address Attribute Determination
TAS is a special, byte-sized, read-modify-write instruction used in synchronization routines. A TAS data access that does not hit in the RAMBAR is non-cacheable and precise. TAS uses the normal effective write protection. If the MMU is enabled, it adds two factors for calculating effective address attributes: Freescale Semiconductor 4-17...
Page 119: Mmu Functionality
(Figure 4-1). Table 4-12. Version 4 Processor Local Bus Memory Pipelines Processor Local Bus Memory Pipeline Stage Instruction Fetch Pipeline Operand Execution Pipeline J stage KC1 stage 4-18 Freescale Semiconductor...
Page 120 MMU structure. At the beginning of the KC1 pipeline stage, the TLB is accessed so the resulting physical address can be sourced to the cache controllers to factor into the cache hit/miss determination. This is required because caches are virtually indexed but physically mapped. Freescale Semiconductor 4-19...
Page 121: Mmu Implementation
TLB allocation address bits (AA[15–6]) are ignored on updates and always read as zero. When the MMUAR register is used for a TLB address, bits FA[5–0] also have this address format. The remaining form address bits (FA[31–6]) are ignored when this register is used for a TLB address. 4-20 Freescale Semiconductor...
Page 122: Tlb Replacement Algorithm
A 1 indicates 03To02 is more recent than 01To00 rdRecent31 A 1 indicates 31 is more recent than 30 rdRecent29 A 1 indicates 29 is more recent than 28 rdRecent27 A 1 indicates 27 is more recent than 26 Freescale Semiconductor 4-21...
Page 123: Tlb Locked Entries
DTLB pages. Because of this, a pool of unlocked TLB entries must be available if virtual memory is used. The above examples show the fewest entries needed to guarantee an instruction can complete execution. For good MMU performance, more unlocked TLB entries should be available. 4-22 Freescale Semiconductor...
Page 124: Mmu Instructions
IC1 or OC1 access control Figure 4-12. Version 4 ColdFire MMU Harvard TLB 4.3.9 MMU Instructions The MOVE to USP and MOVE from USP instructions are added for accessing the USP. Refer to the ColdFire Programmer’s Reference Manual for more information. Freescale Semiconductor 4-23...
Page 125 Freescale Semiconductor...
Page 126: Enhanced Multiply-Accumulate Unit (Emac)
A 48-bit accumulation data path to allow a 40-bit product, plus 8 extension bits increase the dynamic number range when implementing signal processing algorithms The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module (Figure 5-1). Freescale Semiconductor...
Page 127  b 0  x i   b 1  x i 1   b 2  x i 2   b 3  x i 3   – – – – Eqn. 5-2 Freescale Semiconductor...
Page 128: Memory Map/Register Definition
PAVn OMC S/U R/T N V EV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-2. MAC Status Register (MACSR) Freescale Semiconductor...
Page 129 (move.l ACCx,Rx), the lsbs of the 48-bit accumulator logic round the resulting 16- or 32-bit value. If MACSR[S/U] is cleared and MACSR[R/T] is set, the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 16-bit fraction. Freescale Semiconductor...
Page 130: Mask Register (Mask)
This register performs a simple AND with the operand address for MAC instructions. The processor calculates the normal operand address and, if enabled, that address is then ANDed with {0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address Freescale Semiconductor...
Page 131 Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-3. Mask Register (MASK) Table 5-4. MASK Field Descriptions Field Description 31–16 Reserved, must be set. 15–0 Performs a simple AND with the operand address for MAC instructions. MASK Freescale Semiconductor...
Page 132: Accumulator Registers (Acc0-3)
Figure 5-5. Accumulator Extension Register (ACCext01) Table 5-6. ACCext01 Field Descriptions Field Description 31–24 Accumulator 0 upper extension byte ACC0U 23–16 Accumulator 0 lower extension byte ACC0L 15–8 Accumulator 1 upper extension byte ACC1U 7–0 Accumulator 1 lower extension byte ACC1L Freescale Semiconductor...
Page 133: Functional Description
For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator. Freescale Semiconductor...
Page 134 MACSR[6:5] == 01 or 11 /* signed fractional mode */ Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]} if MACSR[6:5] == 10 /* unsigned integer mode */ Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} The four accumulators are represented as an array, ACCn, where n selects the register. Freescale Semiconductor 5-10...
Page 135: Fractional Operation Mode
16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L. • If R0.L is less than 0x8000, the result is truncated to the value of R0.U. • If R0.L is greater than 0x8000, the upper word is incremented (rounded up). 5-11 Freescale Semiconductor...
Page 136 ; save the accumulator extensions move.l accext23,d5 move.l mask,d6 ; save the address mask movem.l #0x00ff,(a7) ; move the state to memory This code performs the EMAC state restore: EMAC_state_restore: Freescale Semiconductor 5-12...
Page 137: Emac Instruction Set Summary
Writes a value to the MASK register move.l MASK,Rx Store MAC Mask Reg Writes the contents of the MASK to a CPU register move.l {Ry,#imm},ACCext01 Loads the accumulator 0,1 extension bytes with a 32-bit Load Accumulator Extensions 01 operand 5-13 Freescale Semiconductor...
Page 138: Emac Instruction Execution Times
Figure 5-9 shows EMAC timing. Three-cycle regBusy stall move move move move move move move EMAC EX1 EMAC EX2 EMAC EX3 EMAC EX4 Accumulator 0 Figure 5-9. EMAC-Specific OEP Sequence Stall Freescale Semiconductor 5-14...
Page 139: Data Representation
The EMAC design includes an additional product/accumulation overflow bit for each accumulator that are treated as sticky indicators and are used to calculate the V bit on each MAC or MSAC instruction. See Section 5.2.1, “MAC Status Register (MACSR)”. 5-15 Freescale Semiconductor...
Page 140 ((product[63:39] != 0x0000_00_0) && (product[63:39] != 0xffff_ff_1)) then { /* product overflow */ MACSR.PAVn = 1 MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then if (product[63] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 Freescale Semiconductor 5-16...
Page 141 MACSR.Z = 1 else MACSR.Z = 0 if ((ACCx[47:31] == 0x0000_0) || (ACCx[47:31] == 0xffff_1)) then MACSR.EV = 0 else MACSR.EV = 1 break; case 1,3: /* signed fractionals */ if (MACSR.OMC == 0 || MACSR.PAVn == 0) 5-17 Freescale Semiconductor...
Page 142 MACSR.Z = 0 if ((ACCx[47:39] == 0x00_0) || (ACCx[47:39] == 0xff_1)) then MACSR.EV = 0 else MACSR.EV = 1 break; case 2: /* unsigned integers */ if (MACSR.OMC == 0 || MACSR.PAVn == 0) then { Freescale Semiconductor 5-18...
Page 143 /* combine with accumulator */ if (MACSR.PAVn == 0) then {if (inst == MSAC) then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0] /* check for accumulation overflow */ if (accumulationOverflow == 1) 5-19 Freescale Semiconductor...
Page 144 /* transfer the result to the accumulator */ ACCx[47:0] = result[47:0] MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if (ACCx[47:32] == 0x0000) then MACSR.EV = 0 else MACSR.EV = 1 break; Freescale Semiconductor 5-20...
Page 145 Enhanced Multiply-Accumulate Unit (EMAC) 5-21 Freescale Semiconductor...
Page 146: Cache
DMA or external devices. This device implements a special branch instruction cache for accelerating branches, enabled by a bit in the cache access control register (CACR[BEC]). The branch cache is described in Section 3.1.1.1, “Change-of-Flow Acceleration.” Freescale Semiconductor...
Page 147: Cache Organization
Set 254 Line Set 255 Cache Line Format Longword 0 Longword 1 Longword 2 Longword 3 Where: TAG—20-bit address tag V—Valid bit for line M—Modified bit for line (data cache only) Figure 6-2. Data Cache Organization and Line Format Freescale Semiconductor...
Page 148: Cache Line States: Invalid, Valid-Unmodified, And Valid-Modified
After the entire cache is flushed, cacheable entries are loaded first in way 0. If way 0 is occupied, the cacheable entry is loaded into the same set in way 1, as shown in Figure 6-3 (D). This process is described in detail in Section 6.4, “Functional Description.” Freescale Semiconductor...
Page 149 0. way 0. be set. The cache should be cache. cleared explicitly by setting CACR[DCINVA] before the cache is enabled. Figure 6-3. Data Cache: A) at Reset; B) after Invalidation; C and D) Loading Pattern Freescale Semiconductor...
Page 150: Memory Map/Register Definition
Data default write-protect. For normal operations that do not hit in the RAMBARs or ACRs, this field defines write-protection. See Section 6.4.1, “Caching Modes.” 0 Not write protected. 1 Write protected. Write operations cause an access error exception. Freescale Semiconductor...
Page 151 Branch cache invalidate all. Invalidation occurs when this bit is set. Branch caches are not cleared on power-up BCINVA or normal reset. 0 No invalidation is performed. 1 Initiate an invalidation of the entire branch cache. 17–16 Reserved, must be cleared. Freescale Semiconductor...
Page 152 1 Supervisor protected. User operations cause a fault Reserved, must be cleared. Enable USP. Enables user stack pointer. EUSP 0 USP disabled. Core uses a single stack pointer. 1 USP enabled. Core uses separate supervisor and user stack pointers. 4–0 Reserved, must be cleared. Freescale Semiconductor...
Page 153: Access Control Registers (Acrn)
1 The upper 8 bits of the address and ACR are compared without a mask function. Address bits [23:20] of the address and ACR are compared using ACR[19:16] as a mask, allowing control of a 1–16 Mbyte memory region. 9–7 Reserved, must be cleared. Freescale Semiconductor...
Page 154: Functional Description
16-Kbyte data cache as an example. This chapter assumes a data cache. Instruction cache operations are similar except for writing to the cache has no support; therefore, such notions of modified cache lines and write allocation do not apply. Freescale Semiconductor...
Page 155 After a line is allocated, the pointer increments to point to the next way. Cache lines from ways 0 and 1 can be protected from deallocation by enabling half-cache locking. If CACR[DHLCK,IHLCK] are set, the replacement pointer is restricted to way 2 or 3. 6-10 Freescale Semiconductor...
Page 156 In this case, an entire line is fetched and stored in the fill buffer. It remains valid there, and the cache can service additional read accesses from this buffer until either another fill or a cache-invalidate-all operation occurs. Freescale Semiconductor 6-11...
Page 157: Caching Modes
Write accesses that hit always write 6-12 Freescale Semiconductor...
Page 158 Before switching cache mode, execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] to invalidate the entire cache. Freescale Semiconductor 6-13...
Page 159: Cache Protocol
The cache controller handles processor writes that miss in the data cache differently for write-through and copyback regions. Write misses to copyback regions cause the cache line to be read from system memory, as shown in Figure 6-7. 6-14 Freescale Semiconductor...
Page 160: Read Hit
For copyback accesses, the cache controller updates the cache line and sets the M bit for the line. An external write is not performed and the cache line state changes to (or remains in) the modified state. Freescale Semiconductor 6-15...
Page 161: Cache Coherency (Data Cache Only)
If a cache miss displaces a modified line, a miss read reference is immediately generated. While waiting for the response, the current contents of the cache location load into the push buffer. When the burst-read 6-16 Freescale Semiconductor...
Page 162: Cache Locking
(B and C) shows, the algorithm for updating the cache and for identifying cache lines for deallocation does not change. If ways 2 and 3 are entirely invalid, cacheable accesses are first allocated in way 2. Way 3 is not used until the location in way 2 is occupied. Freescale Semiconductor 6-17...
Page 163 2 and 3. updated. memory is configured as should not be deallocated. copyback, so updated cache Ways 0 and 1 can be filled lines are marked modified. systematically by using the INTOUCH instruction. Figure 6-8. Data Cache Locking 6-18 Freescale Semiconductor...
Page 164: Cache Management
;increment set index by 1 addq.l #1,d1 ;increment set counter cmpi.l #255,d1 ;are sets for this way done? setloop moveq.l #0,d1 ;set counter to zero again addq.l #1,d0 ;increment to next way move.l d0,a0 ;set = 0, way = d0 Freescale Semiconductor 6-19...
Page 165 ;decrement loop counter bne.b instCacheLoop ;if done, then exit, else continue ; A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache. lock it! move.l #0xa2088800,d0 ;set the instruction cache lock bit 6-20 Freescale Semiconductor...
Page 166: Cache Operation Summary
II5 No action; IV5 No action; invalidate stay in invalid state. go to invalid state. Cache No action; IV6 No action; push stay in invalid state. go to invalid state. IV7 No action; stay in valid state. Freescale Semiconductor 6-21...
Page 167 WV4—CPU write hit WI1—CPU read miss WV7—CPUSHL and Invalid Valid V = 0 V = 1 WV5—DCINVA WV6—CPUSHL and Figure 6-12. Data-Cache Line State Diagram—Write-Through Mode Table 6-6 describes data-cache line transitions and what accesses cause them. 6-22 Freescale Semiconductor...
Page 168 (C,W)V6 No action; Push modified line to push C,W)I7 stay in invalid state. go to invalid state. memory; go to invalid state. (C,W)V7 No action; Push modified line to stay in valid state. memory; go to valid state. Freescale Semiconductor 6-23...
Page 169 Write hit (copyback) Write data to cache; go to modified state. Write hit (write-through) Write data to memory and to cache; stay in valid state. Cache invalidate (C,W)V5 No action; go to invalid state. 6-24 Freescale Semiconductor...
Page 170: Cpushl Enhancements
The extended CPUSHL functionality adds two new bits in the cache control register (CACR) to support a set search using a physical address. In particular, the added CACR bits are defined as: cacr[14] = cacr[SPA] cpushl Search by physical address cacr[20] = cacr[IVO] cpushl Invalidate only Freescale Semiconductor 6-25...
Page 171 – – Cache address/way Invalidate data cpushl dc,(ax) – Physical address Clear data cpushl dc,(ax) – Physical address Push data cpushl dc,(ax) – – Physical address Invalidate data cpushl ic,(ax) – Cache address/way Clear instruction 6-26 Freescale Semiconductor...
Page 172: Initialization/Application Information
The following example sets up the cache for flash or ROM space only. move.l #0xA70C8100,D0 //enable cache, invalidate it, //default mode is cache-inhibited imprecise movec D0, CACR move.l #0xFF00C000,D0 //cache flash space, enable, //ignore supervisor/user, cacheable, writethrough movec D0,ACR0 Freescale Semiconductor 6-27...
Page 173 Cache 6-28 Freescale Semiconductor...
Page 174: Static Ram (Sram)
Features The major features includes: • One 32 Kbyte SRAM • Single-cycle access • Physically located on the processor's high-speed local bus • Memory location programmable on any 0-modulo-32 Kbyte address • Byte, word, and longword address capabilities Freescale Semiconductor...
Page 175: Memory Map/Register Description
SRAM. This creates address aliasing for the on-chip SRAM memory. For example, writes to addresses 0x8000_0000 and 0x8000_8000 modify the same memory location. System software should ensure SRAM address pointers do not exceed the SRAM size to prevent unwanted overwriting of SRAM. Freescale Semiconductor...
Page 176 0 Allows read and write accesses to the SRAM module from non-core masters. 1 Allows only read accesses to the SRAM module from non-core masters. Freescale Semiconductor...
Page 177: Sram Initialization Code
The following code segment describes how to initialize the SRAM. The code sets the base address of the SRAM at 0x8000_0000 and initializes the SRAM to zeros. RAMBASE EQU 0x80000000 ;set this variable to 0x80000000 RAMVALID EQU 0x00000001 Freescale Semiconductor...
Page 178: Power Management
Additionally, if the SRAM contains only instructions, masking operand accesses can reduce power dissipation. Table 7-3 shows examples of typical RAMBAR settings. Table 7-3. Typical RAMBAR Setting Examples Data Contained in SRAM RAMBAR[7:0] Instruction Only 0x2B Data Only 0x35 Instructions and Data 0x21 Freescale Semiconductor...
Page 179 Static RAM (SRAM) Freescale Semiconductor...
Page 180: Introduction
(SBF controls many configuration options, clocks to the SDRAMC, USB, FECs, PCI, and ATA controllers are disabled when the device is in limp mode, and the clocks to individual modules may be disabled via the peripheral power management registers as described in Chapter 9, “Power Management”). Freescale Semiconductor...
Page 181 The SDRAMC, SSI, USB, and real time clock contain some logic that uses the f clock, in addition sys/2 to the module-specific clock. When loading boot code via the SBF, the device is clocked by the main oscillator (f Figure 8-1. Device Clock Connections Freescale Semiconductor...
Page 182: Block Diagram
• Support for low-power modes • Direct clocking of system by input clock, bypassing the PLL • Loss-of-lock reset • Reference crystal oscillator for the real time clock (RTC) module. Input clock used is programmable within the RTC. Freescale Semiconductor...
Page 183: Modes Of Operation
When switching from limp mode to normal functional mode, you must ensure that any peripheral transactions in progress (Ethernet frame reception/transmission) are allowed to complete to avoid data loss or corruption. Freescale Semiconductor...
Page 184: Memory Map/Register Definition
There is also a fast wake-up option for quickly enabling the system clocks during stop recovery (LPCR[FWKUP]). This eliminates the wake-up recovery time but at the risk of sending a potentially unstable clock to the system. Memory Map/Register Definition The PLL programming model consists of the following: Freescale Semiconductor...
Page 185: Pll Control Register (Pcr)
BOOTMOD[1:0] PFDR OUTDIV4 PFDR OUTDIV4 0x06 0x10 01 (Reserved) If FB_AD[6:5]=11, FB_AD[1:0] FB_AD[2:0] (Parallel Boot) Else, PFDR - 1 If SBF_RCON[125]=1, SBF_RCON SBF_RCON (Serial Boot) [119:112] If SBF_RCON[125]=0, [119:112] PFDR - 1 Figure 8-3. PLL Control Register (PCR) Freescale Semiconductor...
Page 186 Note: The OUTDIV3 divider value must be four or eight times the OUTDIV1 divider. For example, if OUTDIV1 equals 0001, then OUTDIV3 must equal 0111 or 1111. FB_CLK must also not exceed 66 MHz. ------------- - ------------------------------------ - Eqn. 8-4 FB_CLK 4 or 8 OUTDIV3 Freescale Semiconductor...
Page 187: Pll Status Register (Psr)
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK LOCKS Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8-4. PLL Status Register (PSR) Freescale Semiconductor...
Page 188: Functional Description
The transition from the old divider value to the new divider value takes no more than 100 ns. Because the output divider transition takes a period of time to change, the PCR may not be written back-to-back without waiting 100 ns between writes. Freescale Semiconductor...
Page 189: Lock Conditions
8.3.3.2 Loss of Lock Interrupt Request By programming the PSR[LOLIRQ] bit, the PLL provides the ability to request an interrupt when a loss-of-lock condition occurs. This bit is sticky, and remains asserted until the user clears the 8-10 Freescale Semiconductor...
Page 190: System Clock Modes
PCI operating frequency. USB_CLKIN in the USB OTG column indicates that the USB On-the-Go module receives its clock from the USB_CLKIN signal rather than the PLL output. Table 8-5. MCF54455 Clocking Scenarios (MHz) ColdFire SDRAMC...
Page 191: Clock Operation During Reset
RESET is negated. The PSR[LOCK] bit is cleared and remains cleared while the PLL is acquiring lock. CAUTION When running in an unlocked state, the clocks the PLL generate are not guaranteed to be stable and may exceed the maximum specified frequency. 8-12 Freescale Semiconductor...
Page 192: Introduction
11.3.4/11-8 0xFC0A_0012 Clock Divider Register (CDR) 0x0001 11.3.5/11-11 User access to supervisor only address locations have no effect and result in a bus error The MISCCR and CDR registers are described in Chapter 11, “Chip Configuration Module (CCM).” Freescale Semiconductor...
Page 193: Wake-Up Control Register (Wcr)
Figure 9-1. Wake-up Control Register (WCR) Table 9-2. WCR Field Descriptions Field Description Enable low-power mode entry. The mode entered is specified in WCR[LPMD]. ENBWCR 0 Low-power mode entry is disabled 1 Low-power mode entry is enabled. Reserved, must be cleared. Freescale Semiconductor...
Page 194: Peripheral Power Management Set Register (Ppmsr0)
PPMR to set, disabling all peripheral module clocks. Reads of these registers return all zeroes. Address: 0xFC04_002C (PPMSR0) Access: Supervisor Write-only SAMCD SMCD Reset: Figure 9-2. Peripheral Power Management Set Register (PPMSR0) Freescale Semiconductor...
Page 195: Peripheral Power Management Clear Register (Ppmcr0)
Because the operation of the crossbar switch and the system control module (SCM) are fundamental to the operation of the device, the clocks for these modules cannot be disabled. Freescale Semiconductor...
Page 196 PIT 2 CD35 PIT 3 CD37 Edge Port CD40 CCM, Reset Controller, Power Management CD41 Pin Multiplexing and Control (GPIO) CD42 PCI Controller CD43 PCI Arbiter CD44 USB On-the-Go CD45 CD46 SDRAM Controller CD47 CD48 ATA Controller CD49 Freescale Semiconductor...
Page 197 CD30 DMA Timer 2 CD31 DMA Timer 3 Table 9-7. PPMHR and PPMLR Field Descriptions Field Description Module slot n clock disable. 0 The clock for this module is enabled. 1 The clock for this module is disabled. Freescale Semiconductor...
Page 198: Low-Power Control Register (Lpcr)
Enabled Disabled Disabled Disabled Enabled Disabled Disabled Disabled Disabled 2–0 Reserved, must be cleared. Functional Description This section discusses the functions and characteristics of the low-power modes, and how each module is affected by, or affects these modes. Freescale Semiconductor...
Page 199: Peripheral Shut Down
An interrupt request which has been enabled at the module of the interrupt’s origin. 9.3.3.1 Run Mode Run mode is the normal system operating mode. Current consumption in this mode is related directly to the system clock frequency. Freescale Semiconductor...
Page 200: Peripheral Behavior In Low-Power Modes
Each module may disable the module clocks locally at the module level, or the module clocks may be individually disabled by the PPMR registers (refer to Section 9.2.4, “Peripheral Power Management Registers (PPMHR0 and PPMLR0)”). In stop mode, all clocks to the system stop. Freescale Semiconductor...
Page 201 CWRI field may enable a core watchdog interrupt and upon a watchdog timeout, this interrupt can bring the device out of low-power mode. This system setup must meet the conditions specified in Section 9.3.3, “Low-Power Modes,” for the core watchdog interrupt to bring the part out of low-power mode. 9-10 Freescale Semiconductor...
Page 202 SDRAM Controller (SDRAMC) SDRAM controller operation is unaffected either the wait or doze modes; however, the SDRAMC is disabled by stop mode. Because the STOP mode disables all clocks to the SDRAMC, the SDRAMC does not generate refresh cycles. Freescale Semiconductor 9-11...
Page 203 In stop mode, the external clock driving EXTAL32K/XTAL32K continues to clock the RTC module. Therefore, the device can update the RTC counters, alarms, etc. while in stop mode. An RTC interrupt/wake-up can be generated while in stop mode to wakeup the device if the RTC alarms are triggered. 9-12 Freescale Semiconductor...
Page 204 In stop mode, the I C module stops immediately and freezes operation, register values, and external pins. Upon exiting stop mode, the I C resumes operation unless stop mode was exited by reset. Freescale Semiconductor 9-13...
Page 205: Summary Of Peripheral State During Low-Power Modes
Stopped SDRAM Controller Enabled Enabled Stopped Fast Ethernet Controller Enabled Interrupt Enabled Interrupt Stopped USB OTG Enabled Interrupt Enabled Interrupt Stopped PCI Controller and Arbiter Enabled Interrupt Enabled Interrupt Stopped ATA Controller Enabled Interrupt Enabled Interrupt Stopped 9-14 Freescale Semiconductor...
Page 206 The JTAG logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any lower-power mode. Upon exit from halt mode, the previous low-power mode is re-entered, and changes made in halt mode remain in effect. Freescale Semiconductor 9-15...
Page 207 Power Management 9-16 Freescale Semiconductor...
Page 208: Introduction
USB-host modules must supply 500 mA with a 5 V supply on its downstream port (referred to as VBUS); however, the USB OTG standard provides a minimum 8 mA VBUS supply requirement. Optionally, the OTG module may supply up to 500 mA to the USB-connected devices. If the connected device attempts Freescale Semiconductor 10-1...
Page 209: Block Diagram
Figure 10-1. USB On-The-Go with on-chip FS/LS Transceiver Interface Block Diagram Figure 10-2 illustrates the On-The-Go (OTG) configuration with an off-chip ULPI transceiver. The ULPI transceiver is an implementation of the HS/FS/LS physical layer which encapsulates the 60+ pin UTMI+ interface using a 12-pin digital interface. 10-2 Freescale Semiconductor...
Page 210: Features
USB device mode — Supports full-speed operation via the on-chip transceiver. — Supports full-speed/high-speed operation via an external ULPI transceiver. — Supports one upstream facing port. — Supports four programmable, bidirectional USB endpoints, including endpoint 0. See endpoint configurations: Freescale Semiconductor 10-3...
Page 211: Modes Of Operation
Stop — The processor stops the clock to the USB OTG module. In this state, the USB OTG module ignores traffic on the USB and does not generate any interrupts or wake-up events. The on-chip transceiver is disabled to save power. • Wait — The clocks to the USB OTG module are running. 10-4 Freescale Semiconductor...
Page 212: External Signal Description
For example, when PHY’s PLL is not stable. State Asserted—PHY has data to transfer to the link. Meaning Negated—PHY has no data to transfer. Timing Synchronous to USB_CLKIN or ULPI_CLK. Freescale Semiconductor 10-5...
Page 213: Usb Otg Control And Status Signals
When the USB OTG module outputs change, the corresponding bits on the UOCSR register are updated, and a maskable interrupt is generated. The UOCSR register is documented in the CCM chapter, see Section 11.3.6, “USB On-the-Go Controller Status Register (UOCSR).” 10-6 Freescale Semiconductor...
Page 214: Memory Map/Register Definition
DM and DP pins when the on-chip transceiver is used. 10.3 Memory Map/Register Definition This section provides the memory map and detailed descriptions of all USB-interface registers. See Table 10-4 for the memory map of the USB OTG interface. Freescale Semiconductor 10-7...
Page 215 0xFC0B_0158 Address at Endpoint List (EPLISTADDR) R/W 0x0000_0000 10.3.4.8/10-28 0xFC0B_015C Host TT Asynchronous Buffer Control (TTCTRL) R/W 0x0000_0000 10.3.4.9/10-28 0xFC0B_0160 Master Interface Data Burst Size (BURSTSIZE) R/W 0x0000_0404 10.3.4.10/10-29 0xFC0B_0164 Host Transmit FIFO Tuning Control (TXFILLTUNING) R/W 0x0000_0000 10.3.4.11/10-29 10-8 Freescale Semiconductor...
Page 216: Module Identification Registers
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 Figure 10-3. Identification Register (ID) Freescale Semiconductor 10-9...
Page 217 PHY width. Indicates data interface to UTMI transceiver. This field is relevant only for UTMI mode; therefore, it is PHYW relevant only to the USB OTG module in UTMI mode. Always reads 00. 00 8-bit data bus (60 MHz) Reserved, always cleared. 2–1 Reserved. For the USB OTG module, always 10. Reserved, always set. 10-10 Freescale Semiconductor...
Page 218 Figure 10-6. Device Hardware Parameters Register (HWDEVICE) Table 10-8. HWDEVICE Field Descriptions Field Description 31–6 Reserved, always cleared. 5–1 Device endpoints. The number of supported endpoints. Always 0x04. DEVEP Indicates the OTG module is device capable. Always set. Freescale Semiconductor 10-11...
Page 219 Reserved. 15–8 Receive address. The number of address bits for the entire RX buffer. Always 0x04. RXADD 7–0 Receive burst. Indicates the number of data beats in a burst for receive DMA data transfers. Always 0x04. RXBURST 10-12 Freescale Semiconductor...
Page 220: Device/Host Timer Registers
Timer run. Enables the general purpose timer. Setting or clearing this bit does not have an effect on the GPTCNT field. 0 Timer stop 1 Timer run Timer reset. Setting this bit reloads GPTCNT with the value in GPTIMERnLD[GPTLD]. 0 No action 1 Load counter value Freescale Semiconductor 10-13...
Page 221: Capability Registers
HCIVERSION register. Address: 0xFC0B_0100 (HCIVERSION) Access: User read-only HCIVERSION Reset Figure 10-11. Host Controller Interface Version Register (HCIVERSION) Table 10-13. HCIVERSION Field Descriptions Field Description 15–0 EHCI revision number. Value is 0x0100 indicating version 1.0. HCIVERSION 10-14 Freescale Semiconductor...
Page 222 Port indicators. Indicates whether the ports support port indicator control. Always cleared. 0 No port indicator fields. 1 The port status and control registers include a R/W field for controlling the state of the port indicator. See Table 10-3 for more information. Freescale Semiconductor 10-15...
Page 223 The feature can be disabled or enabled and set to a specific level by using the asynchronous schedule park mode enable and asynchronous schedule park mode count fields in the USBCMD register. This bit is always set. 0 Park not supported. 1 Park supported. 10-16 Freescale Semiconductor...
Page 224 0 0 0 0 1 0 0 Figure 10-16. Device Control Capability Parameters (DCCPARAMS) Table 10-18. DCCPARAMS Field Descriptions Field Description 31–9 Reserved, always cleared. Host capable. Indicates the USB OTG controller can operate as an EHCI compatible USB 2.0 host. Always set. Freescale Semiconductor 10-17...
Page 225: Operational Registers
0x00 Immediate (no threshold) 0x01 1 microframe 0x02 2 microframes 0x04 4 microframes 0x08 8 microframes 0x10 16 microframes 0x20 32 microframes 0x40 64 microframes Else Reserved See the FS bit description below. This is a non-EHCI bit. 10-18 Freescale Semiconductor...
Page 226 000 1024 elements (4096 bytes) 001 512 elements (2048 bytes) 010 256 elements (1024 bytes) 011 128 elements (512 bytes) 100 64 elements (256 bytes) 101 32 elements (128 bytes) 110 16 elements (64 bytes) 111 8 elements (32 bytes) Freescale Semiconductor 10-19...
Page 227 Software clears certain bits in this register by writing a 1 to them. Address: 0xFC0B_0144 (USBSTS) Access: User read/write NAKI Reset ULPII Reset Figure 10-18. USB Status Register (USBSTS) 10-20 Freescale Semiconductor...
Page 228 USBCMD[PSE] bit have the same value, the periodic schedule is enabled or disabled. Used only in host mode. 0 Disabled. 1 Enabled. Reclamation. DetectS an empty asynchronous schedule. Used only by the host mode. 0 Non-empty asynchronous schedule. 1 Empty asynchronous schedule. Freescale Semiconductor 10-21...
Page 229 (as programmed in the USBCMD[FS] field) is 1024, the frame index register rolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the controller sets this bit each time FRINDEX[12] toggles. Used only in the host mode. 10-22 Freescale Semiconductor...
Page 230 The USB status register (USBSTS) continues to show interrupt sources (even if the USBINTR register disables them), allowing polling of interrupt events by the software. Address: 0xFC0B_0148 (USBINTR) Access: User read/write TIE1 TIE0 UPIE UAIE NAKE Reset ULPIE Reset Figure 10-19. USB Interrupt Enable Register (USBINTR) Freescale Semiconductor 10-23...
Page 231 Interrupt on async advance enable. When this bit and the USBSTS[AAI] bit are set, controller issues an interrupt at the next interrupt threshold. Software clearing the USBSTS[AAI] bit acknowledges the interrupt. Used only in host mode. 0 Disabled 1 Enabled 10-24 Freescale Semiconductor...
Page 232 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-20. Frame Index Register (FRINDEX) Freescale Semiconductor 10-25...
Page 233 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-21. Periodic Frame List Base Address Register (PERIODICLISTBASE) 10-26 Freescale Semiconductor...
Page 234 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-23. Current Asynchronous List Address Register (ASYNCLISTADDR) Freescale Semiconductor 10-27...
Page 235 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-25. Host TT Asynchronous Buffer Control (TTCTRL) 10-28 Freescale Semiconductor...
Page 236 = Standard packet overhead = Time to send data payload = Total packet flight time (send-only) packet (T = Time to fetch packet into TX FIFO up to specified level = Total packet time (fetch and send) packet (T Freescale Semiconductor 10-29...
Page 237 This value is ignored if the USBMODE[SDIS] bit is set. When the USBMODE[SDIS] bit is set, the host controller behaves as if TXFIFOTHRES is set to its maximum value. 15–13 Reserved, must be cleared. 10-30 Freescale Semiconductor...
Page 238 ULPI_ ULPI_ ULPI_ADDR ULPI_DATWR PORT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-28. ULPI Register Access (ULPI VIEWPORT) Freescale Semiconductor 10-31...
Page 239 ULPI_DATRD is valid after ULPI_RUN is cleared. The polling method above can be replaced with interrupts using the ULPI interrupt defined in the USBSTS and USBINTR registers. When a wake-up or read/write operation completes, the ULPI interrupt is set. 10-32 Freescale Semiconductor...
Page 240 PHY into low-power suspend mode and disable the PHY clock. Address: 0xFC0B_0184 (PORTSC1) Access: User read/write PSPD PFSC PHCD WKOC WKDS WLCN Reset SUSP Reset Figure 10-30. Port Status and Control Register (PORTSC1) Freescale Semiconductor 10-33...
Page 241 Wake on connect enable. Enables the port to be sensitive to device connects as wake-up events. WLCN This field is 0 if the PP bit is cleared or the module is in device mode. In host mode, this can work with an external power control circuit. 10-34 Freescale Semiconductor...
Page 242 Device mode: This bit is a read-only status bit. Device reset from the USB bus is also indicated in the USBSTS register. 0 Port is not in reset. 1 Port is in reset. Freescale Semiconductor 10-35...
Page 243 Over-current active. This bit automatically transitions from 1 to 0 when the over-current condition is removed. For host/OTG implementations, the user can provide over-current detection to the USBn_PWRFAULT signal for this condition. For device-only implementations, this bit must always be cleared. 0 Port not in over-current condition. 1 Port currently in over-current condition. 10-36 Freescale Semiconductor...
Page 244 The status inputs de-bounce using a 1 ms time constant. Values on the status inputs that do not persist for more than 1 ms do not cause an update of the status inputs or an OTG interrupt. Freescale Semiconductor 10-37...
Page 245 1 millisecond timer interrupt status. This bit is set once every millisecond. Software must write a 1 to clear this bit. 1MSS B session end interrupt status. Indicates when VBUS falls below the B session end threshold. Software must write BSEIS a 1 to clear this bit. 10-38 Freescale Semiconductor...
Page 246 1 The pull-up on DP is asserted for data pulsing during SRP. OTG Termination. This bit must be set with the OTG module in device mode. 0 Disable pull-down on DM. 1 Enable pull-down on DM. Reserved, must be cleared. Freescale Semiconductor 10-39...
Page 247 Setup lockout mode. For the module in device mode, this bit controls behavior of the setup lock mechanism. See SLOM Section 10.5.3.4.4, “Control Endpoint Operation.” 0 Setup lockouts on. 1 Setup lockouts off (software requires use of the USBCMD[SUTW] bit). 10-40 Freescale Semiconductor...
Page 248 PETB PERB Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-34. Endpoint Initialization Register (EPPRIME) Freescale Semiconductor 10-41...
Page 249 FERB[3] corresponds to endpoint 3. 10.3.4.20 Endpoint Status Register (EPSR) This register is not defined in the EHCI specification. This register is only used in device mode. 10-42 Freescale Semiconductor...
Page 250 If the corresponding IOC bit is set in the transfer descriptor, this bit is set simultaneously with the USBINT. Writing a 1 clears the corresponding bit in this register. ETCE[3] (bit 19) corresponds to endpoint 3. Freescale Semiconductor 10-43...
Page 251 0 Endpoint OK 1 Endpoint stalled 15–8 Reserved, must be cleared. RX endpoint enable. Endpoint zero is always enabled. 1 Enabled. 6–4 Reserved, must be cleared. 3–2 RX endpoint type. Endpoint zero is always a control endpoint. 00 Control 10-44 Freescale Semiconductor...
Page 252 TX data toggle inhibit. This bit is used only for test and should always be written as 0. Writing a 1 to this bit causes this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet. 0 PID sequencing enabled. 1 PID sequencing disabled. Reserved, must be cleared. Freescale Semiconductor 10-45...
Page 253 Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host. It continues returning STALL until software clears this bit or automatically clears as above, 0 Endpoint OK 1 Endpoint stalled 10-46 Freescale Semiconductor...
Page 254: System Interface
The USB OTG module may interface to any ULPI compatible PHY as well. Due to pin-count limitations the USB module only supports certain combinations of PHY interfaces and USB functionality. Refer to the Table 10-43 for more information. Freescale Semiconductor 10-47...
Page 255: Initialization/Application Information
USB modules; however, full details of the EHCI specification are beyond the scope of this document. 10.5.1.1 Host Controller Initialization After initial power-on or module reset (via the USBCMD[RST] bit), all of the operational registers are at default values, as illustrated in the register memory map in Table 10-4. 10-48 Freescale Semiconductor...
Page 256: Device Data Structures
The USB OTG uses an array of device endpoint queue heads to organize device transfers. As shown in Figure 10-40, there are two endpoint queue heads in the array for each device endpoint—one for IN and one for OUT. The EPLISTADDR provides a pointer to the first entry in the array. Freescale Semiconductor 10-49...
Page 257 While a packet is in progress, the overlay area of the dQH acts as a staging area for the dTD so the device controller can access needed information with minimal latency. Figure 10-41 shows the endpoint queue head structure. 10-50 Freescale Semiconductor...
Page 258 Maximum Packet Length (dQH) and the Total Bytes field (dTD) 01 Execute 1 Transaction. 10 Execute 2 Transactions. 11 Execute 3 Transactions. Note: Non-ISO endpoints must set Mult equal to 00. ISO endpoints must set Mult equal to 01, 10, or 11 as needed. Freescale Semiconductor 10-51...
Page 259 Until a transfer expires, software must not write the queue head overlay area or the associated transfer descriptor. When the transfer is complete, the device controller writes the results back to the original transfer descriptor and advance the queue. 10-52 Freescale Semiconductor...
Page 260 Device controller read/write; all others read-only. Figure 10-42. Endpoint Transfer Descriptor (dTD) 10.5.2.2.1 Next dTD Pointer (Offset = 0x0) The next dTD pointer is used to point the device controller to the next dTD in the linked list. Freescale Semiconductor 10-53...
Page 261 For OUT transfers the total bytes must be evenly divisible by the maximum packet length. Interrupt on complete. Indicates if USBSTS[UI] is set in response to device controller finished with this dTD. 14–12 Reserved. Reserved for future use and must be cleared. 10-54 Freescale Semiconductor...
Page 262 Current Offset. Offset into the 4kB buffer where the packet begins. Current Offset 1;10–0 Frame Number. Written by the device controller to indicate the frame number a packet finishes in. Typically Frame Number correlates relative completion times of packets on an ISO endpoint. Freescale Semiconductor 10-55...
Page 263: Device Operation
It is not necessary to initially prime endpoint 0 because the first packet received is always a setup packet. The contents of the first setup packet requires a response in accordance with USB device framework command set. 10-56 Freescale Semiconductor...
Page 264 Bus Inactive Configured Suspend FS/HS FS/HS Bus Activity Software-only state Figure 10-43. USB 2.0 Device States States powered, attach, defaultFS/HS, suspendFS/HS are implemented in the USB OTG, and they are communicated to the DCD using these status bits: Freescale Semiconductor 10-57...
Page 265 DCD processes a USB reset event, it is likely w3a4no dTDs have been allocated. 6. At this time, the DCD may release control back to the OS because no further changes to the device controller are permitted until a port change detect is indicated. 10-58 Freescale Semiconductor...
Page 266 (one more devices) back to the active condition. NOTE Before use of resume signaling, the host must enable it by using the set feature command defined in chapter 9 Device Framework of the USB 2.0 specification. Freescale Semiconductor 10-59...
Page 267 Data Toggle Reset (TXR, RXR) 1 Synchronize the data PIDs Data Toggle Inhibit (TXI, RXI) 0 PID sequencing disabled Endpoint Type (TXT, RXT) 00 Control 01 Isochronous 10 Bulk 11 Interrupt Endpoint Stall (TXS, RXS) 0 Not stalled 10-60 Freescale Semiconductor...
Page 268 The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device controller by setting the data toggle reset bit in the EPCRn register. This should only happen when configuring/initializing an endpoint or returning from a STALL condition. Freescale Semiconductor 10-61...
Page 269 After a priming request is complete, an endpoint state of primed is indicated in the EPSR register. For a primed transmit endpoint, the device controller can respond to an IN request from the host and meet the stringent bus turnaround time of high-speed USB. 10-62 Freescale Semiconductor...
Page 270 — Table 10-54. Variable Length Transfer Protocol Example (ZLT=1) Bytes Max. Packet (dTD) Length (dQH) — — — — NOTE The MULT field in the dQH must be set to 00 for bulk, interrupt, and control endpoints. Freescale Semiconductor 10-63...
Page 271 Table 10-55. Interrupt/Bulk Endpoint Bus Response Matrix Token Stall Primed Underflow Overflow Type Primed Ignore Ignore Ignore Setup STALL Transmit BS Error STALL Receive + NYET/ACK STALL Ping Ignore Ignore Ignore Ignore Ignore Invalid Force bit stuff error 10-64 Freescale Semiconductor...
Page 272 If a new setup packet is indicated after the EPPRIME bit is cleared, then the transfer descriptor can be freed and the DCD must re-interpret the setup packet. Freescale Semiconductor 10-65...
Page 273 Isochronous endpoints used for real-time scheduled delivery of data, and their operational model is significantly different than the host throttled bulk, interrupt, and control data pipes. Real time delivery by the USB OTG is accomplished by: • Exactly MULT packets per (micro)frame are transmitted/received. 10-66 Freescale Semiconductor...
Page 274 • TX packet retired: — MULT counter reaches zero. — Fulfillment error (transaction error bit is set): – # packets occurred > 0 AND # packets occurred < MULT Freescale Semiconductor 10-67...
Page 275 SOF for packet N is received. Isochronous Endpoint Bus Response Matrix Table 10-57. Isochronous Endpoint Bus Response Matrix Token Stall Primed Underflow Overflow Type Primed STALL STALL STALL Setup NULL NULL Transmit BS Error Packet Packet 10-68 Freescale Semiconductor...
Page 276 Section 10.5.3.4, “Packet Transfers,” the dQH also contains the following parameters for the associated endpoint: multipler, maximum packet length, and interrupt on setup. The next section includes demonstration of complete initialization of the dQH including these fields. Freescale Semiconductor 10-69...
Page 277 Existing control packets in progress must be flushed and the new control packet completed. 4. Decoding setup packet and prepare data phase (optional) and status phase transfer as required by the USB specification chapter 9 or application specific protocol. 10-70 Freescale Semiconductor...
Page 278 6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer. 7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer pointers. Freescale Semiconductor 10-71...
Page 279 Active = 0, Halted = 0, Transaction error = 0, Data buffer error = 0 Should any combination other than the one shown above exist, the DCD must take proper action. Transfer failure mechanisms are indicated in Section 10.5.3.6.6, “Device Error Matrix.” 10-72 Freescale Semiconductor...
Page 280 ISO Packet Error ISO Fulfillment Error Both The device controller manages all errors on bulk/control/interrupt endpoints except for a data buffer overflow. However, for ISO endpoints, errors packets are not retried and errors are tagged as indicated. Freescale Semiconductor 10-73...
Page 281: Servicing Interrupts
Table 10-61. Low Frequency Interrupt Events Interrupt Action Port Change Change software state information. Sleep Enable (Suspend) Change software state information. Low power managing as necessary. Reset Received Change software state information. Abort pending transfers. 10-74 Freescale Semiconductor...
Page 282: Deviations From The Ehci Specifications
10.5.5.1.1 Capability Registers These additions to the capability registers support the embedded Transaction translator function: • N_TT added to HSCPARAMS - Host Controller Structural Parameters • N_PTT added to HSCPARAMS - Host Controller Structural Parameters Freescale Semiconductor 10-75...
Page 283 It is demonstrated here how hub address and endpoint speed fields should be set for directly attached FS/LS devices and hubs: 1. QH (for direct attach FS/LS) – asynchronous (bulk/control endpoints) periodic (interrupt) • Hub address equals 0 • Transactions to direct attached device/hub. 10-76 Freescale Semiconductor...
Page 284 After periodic transfers are exhausted, any stored asynchronous transfer is moved. Asynchronous transfers are opportunistic because they execute when possible and their operation is not tied to H-frame and B-frame boundaries with the exception that an asynchronous transfer cannot babble through the SOF (start of B-frame 0.) Freescale Semiconductor 10-77...
Page 285 – EOF (and not started in microframes 6) – Idle for more than 4 microframes — Abort of pending complete-splits – EOF – Idle for more than 4 microframes • USB 2.0 - 11.18.[7-8] — Transaction tracking for up to 4 data pipes. 10-78 Freescale Semiconductor...
Page 286 PCI configuration registers. Starts of microframes are timed precisely to 125 µs using the transceiver clock as a reference clock or a 60 Mhz transceiver clock for 8-bit physical interfaces and full-speed serial interfaces. Freescale Semiconductor 10-79...
Page 287 • A 1-bit high-speed indicator bit has been added to PORTSCn to signify that the port is in HS vs. FS/LS. — This information is redundant with the 2-bit port speed indicator field above. 10-80 Freescale Semiconductor...
Page 288: Introduction
32-bit data bus and 24 address lines. The available bus control signals include R/W, TS, TA, OE, and BE/BWE[3:0]. Up to four chip selects can be programmed to select and control external devices and to provide bus cycle termination. Freescale Semiconductor 11-1...
Page 289: External Signal Descriptions
Table 11-3. CCM Memory Map Width Address Register Access Reset Value Section/Page (bits) Supervisor Access Only Registers 0xFC0A_0004 Chip Configuration Register (CCR) See Section 11.3.1/11-3 0xFC0A_0008 Reset Configuration Register (RCON) 0x03ED_0346 11.3.2/11-7 0xFC0A_000A Chip Identification Register (CIR) See Section 11.3.3/11-8 11-2 Freescale Semiconductor...
Page 290: Chip Configuration Register (Ccr)
Note: Reset value depends upon chosen reset configuration. Default reset value (BOOTMOD = 00) is the value of RCON. Figure 11-2. Chip Configuration Register (CCR) 360-pin Table 11-4. CCR Field Descriptions 360-pin Field Description 15–10 Reserved, must be cleared. 9–8 Reserved, must be set. Freescale Semiconductor 11-3...
Page 291 PCI host/agent mode, if the PCI is enabled. Reflects whether the PCI is a host or agent. PCIMODE 0 PCI is agent (FBCONFIG = 1 PCI is host 011, 111) Oscillator clock mode, if the PCI is disabled. OSCMODE 0 Crystal oscillator mode (FBCONFG  1 Oscillator bypass mode 011, 111) 11-4 Freescale Semiconductor...
Page 292 (values used to divide the VCO clock down to the system clocks) are shown in the below table. OUTDIV Clock PLL clock PODR Value OUTDIV1 System bus OUTDIV2 Flexbus (FB_CLK) OUTDIV3 PCI clock OUTDIV4 MULT MULT USB clock OUTDIV5 The value of MULT is the reference clock multiplier selected by the CCR[PLLMULT] field. Freescale Semiconductor 11-5...
Page 293 PLL mode. Reflects the chosen overall clocking mode for the device. PLLMODE 0 Normal operation; PLL drives internal clocks 1 Limp mode; low-power clock divider drives internal clocks 11-6 Freescale Semiconductor...
Page 294: Reset Configuration Register (Rcon)
11-5. Only two versions are available, unlike three versions for the CCR, because there are only two sets of default values. Those default values make one of the three CCR versions (360-pin PCI-disabled) unavailable as a default configuration. Freescale Semiconductor 11-7...
Page 295: Chip Identification Register (Cir)
0x04F MCF54450 0x04D MCF54451 0x04B MCF54452 0x049 MCF54453 0x04A MCF54454 0x048 MCF54455 5–0 Part revision number. This number increases by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order. 11.3.4 Miscellaneous Control Register (MISCCR) The MISCCR register provides clock source selection and configuration for internal clocks, as well as SSI/timer DMA mux control and other miscellaneous control functionality.
Page 296 PLL begins the process of relocking and driving the system clocks. Bus monitor external enable bit. Enables the bus monitor to operate during external FlexBus cycles 0 Bus monitor disabled on external FlexBus cycles 1 Bus monitor enabled on external FlexBus cycles Freescale Semiconductor 11-9...
Page 297 USB clock source. Selects between the PLL and the external USB_CLKIN external pin as the clock source for USBSRC the serial and ULPI interfaces of the USB module. 0 USB_CLKIN pin drives USB serial interface clocks. 1 PLL drives USB serial interface clocks. 11-10 Freescale Semiconductor...
Page 298: Clock-Divider Register (Cdr)
USB OTG module. Address: 0xFC0A_0014 (UOCSR) Access: Supervisor read/write CRG_ DCR_ DPPD DMPD DPPU VBUS VBUS AVLD BVLD VVLD SEND WKUP UOMIE XPDE Reset Figure 11-9. USB On-the-Go Controller Status Register (UOCSR) Freescale Semiconductor 11-11...
Page 299 1 Interrupt sources are enabled. On-chip transceiver pull-down enable. XPDE 0 50 k pull-downs disabled on OTG D+ and D- pins of on-chip transceiver. 1 On-chip 50 k pull-downs enabled on OTG D+ and D- transceiver pins of on-chip transceiver. 11-12 Freescale Semiconductor...
Page 300: Reset Configuration
NOTE The logic levels for reset configuration on FB_AD[7:0] must be actively driven when BOOTMOD equals 10. The FB_AD[15:8] pins must be allowed to float or be pulled high. Freescale Semiconductor 11-13...
Page 301 Limp mode PLL mode PCI Host/Agent Mode FB_AD3 (360-pin PCI-Enabled Devices) (none) See RCON[3] PCI host mode PCI agent mode Oscillator Mode FB_AD3 (360-pin PCI-Disabled Devices and 256-pin Devices) (none) See RCON[3] Oscillator bypass mode Crystal oscillator mode 11-14 Freescale Semiconductor...
Page 302 SPI memory through serial boot using the SBF_DI, SBF_DO, SBF_CS, and SBF_CK signals. The internal configuration signals are driven to reflect the data being received from the external SPI memory to allow for module configuration. See Chapter 12, “Serial Boot Facility (SBF),” more details on serial boot. Freescale Semiconductor 11-15...
Page 303 See RCON[3] Oscillator bypass mode Crystal oscillator mode SBF_RCON[123] Bus Monitor Enable (none) See MISCCR[11] Bus monitor enabled Bus monitor disabled SBF_RCON[122:120] Bus Monitor Timeout (FB_CLK Cycles) 65536 32768 16384 (none) See MISCCR[10:8] 8192 4096 2048 1024 11-16 Freescale Semiconductor...
Page 304 SSI_CLKIN pin drives SSI clock SBF_RCON[104] PCI Pad Slew Rate Mode (none) See RCON[2] 66 MHz slew rate mode 33 MHz slew rate mode SBF_RCON[103] PCI Interrupt See RCON[3] - (none) host mode disables PCI interrupt enabled interrupt PCI interrupt disabled Freescale Semiconductor 11-17...
Page 305 BAR0 disabled (none) $5807 SBF_RCON[95:80] PCI Device ID (none) $1957 SBF_RCON[79:64] PCI Vendor ID (none) $068000 SBF_RCON[63:40] PCI Class Code (none) SBF_RCON[39:32] PCI Revision ID (none) $0000 SBF_RCON[31:16] PCI Subsystem ID (none) $0000 SBF_RCON[15:0] PCI Subsystem Vendor ID 11-18 Freescale Semiconductor...
Page 306: Boot Configuration
During reset configuration, the FB_CS0 chip select pin is always configured to select an external boot device. The valid (V) bit in the CSMR0 register is ignored and FB_CS0 is enabled after reset. FB_CS0 is asserted for the initial boot fetch accessed from address 0x0000_0000 for the stack pointer and address Freescale Semiconductor 11-19...
Page 307: Low Power Configuration
Low Power Configuration After reset, the device can be configured for operation during the low power modes using the low power control register (LPCR). For more information on this register, see Section 9.2.5, “Low-Power Control Register (LPCR).” 11-20 Freescale Semiconductor...
Page 308: Introduction
SPI memory clock frequency, configures an extended set of power-up options for the processor, and optionally loads code into the on-chip SRAM. Through interaction with the reset controller, the SBF performs these actions so that the chip is properly configured after exiting the reset state. Freescale Semiconductor 12-1...
Page 309: Features
The SBF programming model consists of the registers listed below. Table 12-2. SBF Memory Map Width Address Register Access Reset Value Section/Page (bits) 0xFC0A_0018 Serial boot facility status register (SBFSR) See Section 12.3.1/12-3 0xFC0A_0020 Serial boot facility control register (SBFCR) See Section 12.3.2/12-3 12-2 Freescale Semiconductor...
Page 310: Serial Boot Facility Status Register (Sbfsr)
BLDIV field is written. Any subsequent writes to this field prior to a power-on reset event terminate without effect. 0 SBF uses the standard command READ 1 SBF uses the FAST_READ command Freescale Semiconductor 12-3...
Page 311: Functional Description
3. The weak internal pull-up on SBF_DI is enabled. This allows a 1-to-0 transition to register when the SPI memory output switches from high-impedance to logic 0. 4. The SBF shifts the standard SPI memory read command (0x03) followed by repeated 0x00 address  60. bytes to the SPI memory at f 12-4 Freescale Semiconductor...
Page 312: Reset Configuration And Optional Boot Load
Although the SBF permits up to 65,536 longwords (262,144 bytes) to be loaded, the maximum practical number that can be read is limited by the size of the device’s internal SRAM (8192 longwords (32,768 bytes) for this device). Freescale Semiconductor 12-5...
Page 313: Execution Transfer
12-6, depending on the exact device used (256- or 360-pin). See Section 11.4.1.3, “Reset Configuration (BOOTMOD[1:0] = 11),” for the reset configuration (SBF_RCON) data definition. Table 12-5. SPI Memory Organization (360-pin Devices) Byte Address Data Contents {0000,BLDIV[3:0]} BLL[7:0] BLL[15:8] RCON[7:0] RCON[15:8] 0x12 RCON[127:120] 0x13 CODE_BYTE_0 0x14 CODE_BYTE_1 12-6 Freescale Semiconductor...
Page 314: Fast_Read Feature Initialization
To enable the FAST_READ feature, set SBFCR[FR] in the same write that sets the SBFCR[BLDIV] field. The value written to SBFCR[BLDIV] should correspond to the frequency the SPI memory supports in FAST_READ mode. After a soft reset, Freescale Semiconductor 12-7...
Page 315 FAST_READ feature altogether. Even when the delays within the processor itself are minimized, the actual SPI memories may have similarly untenable electrical specifications (data input setup and output valid times). 12-8 Freescale Semiconductor...
Page 316: Introduction
— External — Power-on reset (POR) — Core watchdog timer — Phase locked-loop (PLL) loss of lock — Software • Software-assertable RSTOUT pin independent of chip-reset state • Software-readable status flags indicating the cause of the last reset Freescale Semiconductor 13-1...
Page 317: External Signal Description
0xFC0A_0000 Reset Control Register (RCR) 0x00 13.3.1/13-2 0xFC0A_0001 Reset Status Register (RSR) See Section 13.3.2/13-3 13.3.1 Reset Control Register (RCR) The RCR allows software control for requesting a reset and for independently asserting the external RSTOUT pin. 13-2 Freescale Semiconductor...
Page 318: Reset Status Register (Rsr)
RSR can be read at any time. Writing to RSR has no effect. Address: 0xFC0A_0001 (RSR) Access: User read-only SOFT CORE Reset: Reset Reset Reset Reset Reset Dependent Dependent Dependent Dependent Dependent Figure 13-3. Reset Status Register (RSR) Freescale Semiconductor 13-3...
Page 319: Reset Sources
Reset is then asserted on the next rising edge of the system clock after the cycle is terminated. Internal byte, word, or longword writes are guaranteed to complete without data corruption when a synchronous reset occurs. External writes, including longword writes to 16-bit ports, are also guaranteed to complete. 13-4 Freescale Semiconductor...
Page 320: Reset Control Flow
The reset logic control flow is shown in Figure 13-4. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate. Freescale Semiconductor 13-5...
Page 321 BOOTMOD[1:0] == 10? from FB_AD[7:0] pins (Parallel RCON) Figure 13-4. Reset Control Flow 13.4.2.1 Synchronous Reset Requests In this discussion, the reference in parentheses refer to the state numbers in Figure 13-4. All cycle counts given are approximate. 13-6 Freescale Semiconductor...
Page 322: Concurrent Resets
If other reset sources are asserted after the RSR status bits have been latched (4 or 5), the device is held in reset (9 or 10) until all sources have negated, and the subsequent sources are not reflected in the RSR contents. Freescale Semiconductor 13-7...
Page 323 Reset Controller Module 13-8 Freescale Semiconductor...
Page 324: Introduction
— SCM interrupt status register (SCMISR) to service a bus fault or watchdog interrupt — Bus monitor timeout register (BMT) • Core fault reporting registers 14.2 Memory Map/Register Definition The memory map for the SCM registers is shown in Table 14-1. Freescale Semiconductor 14-1...
Page 325: Master Privilege Register (Mpr)
Reset 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Figure 14-1. Master Privilege Register (MPR) 14-2 Freescale Semiconductor...
Page 326 1 This master is trusted for write accesses. Master privilege level. Determines how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. Freescale Semiconductor 14-3...
Page 327: Peripheral Access Control Registers (Pacrx)
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 Figure 14-7. Peripheral Access Control Register E (PACRE) 14-4 Freescale Semiconductor...
Page 328 PACR18 Interrupt Controller 0 PACR19 Interrupt Controller 1 PACR21 Interrupt Controller IACK PACR22 PACR23 DSPI PACR24 UART0 PACR25 UART1 PACR26 UART2 PACR28 DMA Timer 0 PACR29 DMA Timer 1 PACR30 DMA Timer 2 PACR31 DMA Timer 3 Freescale Semiconductor 14-5...
Page 329 1 This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor access attribute, and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 14-6 Freescale Semiconductor...
Page 330: Core Watchdog Control Register (Cwcr)
CWRWH 0 Core watchdog timer stops counting if the core is halted. 1 Core watchdog timer continues to count even while the core is halted. Core watchdog timer enable. 0 CWT is disabled. 1 CWT is enabled. Freescale Semiconductor 14-7...
Page 331: Core Watchdog Service Register (Cwsr)
0x55 or 0xAA causes an immediate system reset, regardless of the value in the CWCR[CWRI] field. Address: 0xFC04_001B (CWSR) Access: User read/write CWSR Reset: — — — — — — — — Figure 14-12. Core Watchdog Service Register (CWSR) 14-8 Freescale Semiconductor...
Page 332: Scm Interrupt Status Register (Scmisr)
Core watchdog interrupt flag. Indicates whether an CWT interrupt has occurred. Writing a 1 clears this bit and CWIC negates the interrupt request. Writing a 0 has no effect. 0 No CWT interrupt has occurred. 1 CWT interrupt has occurred. Freescale Semiconductor 14-9...
Page 333: Burst Configuration Register (Bcr)
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 14-15. Core Fault Address Register (CFADR) 14-10 Freescale Semiconductor...
Page 334: Core Fault Interrupt Enable Register (Cfier)
14.2.9 Core Fault Location Register (CFLOC) The read-only CFLOC register indicates the exact location within the device of the captured fault information. Address: 0xFC04_0076 (CFLOC) Access: User read-only Reset: – Figure 14-17. Core Fault Location Register (CFLOC) Freescale Semiconductor 14-11...
Page 335: Core Fault Attributes Register (Cfatr)
Reserved, must be cleared. Indicates the mode the device was in during the last faulted core access. MODE 0 User mode 1 Supervisor mode Defines the type of last faulted core access. TYPE 0 Instruction 1 Data 14-12 Freescale Semiconductor...
Page 336: Access Control
If this periodic servicing action does not occur, the timer expires and, depending on the setting of CWCR[CWRI], different events may occur: • An interrupt may be generated to the core. • An immediate system reset. Freescale Semiconductor 14-13...
Page 337: Core Data Fault Recovery Registers
The details on the core fault recovery registers are provided in the above sections. It is important to note these registers are used to capture fault recovery information on any processor-initiated system bus cycle terminated with an error. 14-14 Freescale Semiconductor...
Page 338: Overview
Fast Ethernet Fast Ethernet USB On-the-Go Serial Boot Core Controller Controller 0 Controller 1 Module Master Modules Crossbar Switch Slave Modules SDRAM SRAM Other On-chip FlexBus Controller Slave Peripherals Backdoor Figure 15-1. Bus Architecture Block Diagram Freescale Semiconductor 15-1...
Page 339 (e.g., cacheable, non-cacheable). For this device, one possible configuration defines the default memory attribute as non-cacheable, and one ACR then identifies cacheable addresses, e.g., ADDR[31] equals 0 identifies the cacheable space. 15-2 Freescale Semiconductor...
Page 340: Features
Access Reset Value Section/Page (bits) 0xFC00_4100 Priority Register Slave 1 (XBS_PRS1) 0x6540_3210 15.4.1/15-4 0xFC00_4110 Control Register Slave 1 (XBS_CRS1) 0x0000_0000 15.4.2/15-5 0xFC00_4200 Priority Register Slave 2 (XBS_PRS2) 0x6540_3210 15.4.1/15-4 0xFC00_4210 Control Register Slave 2 (XBS_CRS2) 0x0000_0000 15.4.2/15-5 Freescale Semiconductor 15-3...
Page 341: Xbs Priority Registers (Xbs_Prsn)
Reset 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Figure 15-2. XBS Priority Registers Slave n (XBS_PRSn) 15-4 Freescale Semiconductor...
Page 342: Xbs Control Registers (Xbs_Crsn)
The XBS control registers (XBS_CRSn) control several features of each slave port and must be accessed using 32-bit accesses. After XBS_CRSn[RO] is set, the XBS_CRSn can only be read; attempts to write to it have no effect and result in an error response. Freescale Semiconductor 15-5...
Page 343 010 Park on master port M2 (FEC0) 011 Park on master port M3 (FEC1) 100 Reserved 101 Park on master port M5 (PCI Controller) 110 Park on master port M6 (USB OTG) 111 Park on master port M7 (Serial Boot) 15-6 Freescale Semiconductor...
Page 344: Functional Description
Handoff occurs to the next master in line after one cycle of arbitration. If the slave port is put into low-power park mode, the round-robin pointer is reset to point at master port 0, giving it the highest priority. Freescale Semiconductor 15-7...
Page 345: Initialization/Application Information
No initialization is required by or for the crossbar switch. Hardware reset ensures all the register bits used by the crossbar switch are properly initialized to a valid state. Settings and priorities should be programmed to achieve maximum system performance. 15-8 Freescale Semiconductor...
Page 346: Introduction
The GPIO functionality of the port IRQ pins is selected by the edge port module. They are shown in the figure only for completeness. This chapter also includes registers for controlling the drive strengths and slew rates of the external pins. Freescale Semiconductor 16-1...
Page 347 Port FB_AD[15:8] / PFBADML[7:0] Port FBADML IRQ4 / SSI_CLKIN / PIRQ4 IRQ3 / PIRQ3 IRQ1 / PCI_INTA / PIRQ1 Port FB_AD[7:0] / PFBADL[7:0] FBADL Pin Assignment and Drive Strength Control Internal Bus Figure 16-1. Ports Block Diagram 16-2 Freescale Semiconductor...
Page 348: Overview
(i.e., FB_AD23), while designations for multiple signals within a group use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. Freescale Semiconductor 16-3...
Page 349 ATA_RESET GPIO ATA reset Table 16-2. MCF5445x Signal Information and Muxing MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA Reset RESET — — — EVDD RSTOUT — — — — EVDD...
Page 350 Table 16-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA FB_AD[31:24] PFBADH[7:0] FB_D[31:24] — — EVDD A14, A13, D12, J2, K4, J1, K1–3, C12, B12, A12,...
Page 351 Pin Multiplexing and Control Table 16-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA PCI_GNT0/ PPCI4 — — — EVDD — PCI_EXTREQ PCI_IDSEL — —...
Page 352 Pin Multiplexing and Control Table 16-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA SD_WE — — — — SDVDD External Interrupts Port IRQ7 PIRQ7 —...
Page 353 Pin Multiplexing and Control Table 16-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA FEC1_RXCLK PFEC1H3 — ATA_DATA5 — EVDD — FEC1_RXDV PFEC1H2 FEC1_RMII_ ATA_DATA15 —...
Page 354 Pin Multiplexing and Control Table 16-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA SSI_MCLK PSSI4 — — — EVDD SSI_BCLK PSSI3 U1CTS — —...
Page 355 Pin Multiplexing and Control Table 16-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA U0RXD PUART1 — — — EVDD AB16 U0TXD PUART0 — —...
Page 356 Pin Multiplexing and Control Table 16-2. MCF5445x Signal Information and Muxing (continued) MCF54452 MCF54450 MCF54453 Signal Name GPIO Alternate 1 Alternate 2 MCF54451 MCF54454 256 MAPBGA MCF54455 360 TEPBGA VDD_RTC — — — — — — — — — —...
Page 357: Memory Map/Register Definition
16.3.1/16-16 0xFC0A_400F PODR_ATAL 0x07 16.3.1/16-16 0xFC0A_4010 PODR_FEC1H 0xFF 16.3.1/16-16 0xFC0A_4011 PODR_FEC1L 0xFF 16.3.1/16-16 0xFC0A_4014 PODR_FBADH 0xFF 16.3.1/16-16 0xFC0A_4015 PODR_FBADMH 0xFF 16.3.1/16-16 0xFC0A_4016 PODR_FBADML 0xFF 16.3.1/16-16 0xFC0A_4017 PODR_FBADL 0xFF 16.3.1/16-16 Port Data Direction Registers 0xFC0A_4018 PDDR_FEC0H 0x00 16.3.2/16-18 16-12 Freescale Semiconductor...
Page 358 See Section 16.3.3/16-20 0xFC0A_4034 PPDSDR_BE See Section 16.3.3/16-20 0xFC0A_4035 PPDSDR_CS See Section 16.3.3/16-20 0xFC0A_4036 PPDSDR_DMA See Section 16.3.3/16-20 0xFC0A_4037 PPDSDR_FECI2C See Section 16.3.3/16-20 0xFC0A_4039 PPDSDR_UART See Section 16.3.3/16-20 0xFC0A_403A PPDSDR_DSPI See Section 16.3.3/16-20 0xFC0A_403B PPDSDR_TIMER See Section 16.3.3/16-20 Freescale Semiconductor 16-13...
Page 359 16.3.4/16-23 0xFC0A_4055 PCLRR_USB 0x00 16.3.4/16-23 0xFC0A_4056 PCLRR_ATAH 0x00 16.3.4/16-23 0xFC0A_4057 PCLRR_ATAL 0x00 16.3.4/16-23 0xFC0A_4058 PCLRR_FEC1H 0x00 16.3.4/16-23 0xFC0A_405A PCLRR_FEC1L 0x00 16.3.4/16-23 0xFC0A_405C PCLRR_FBADH 0x00 16.3.4/16-23 0xFC0A_405D PCLRR_FBADMH 0x00 16.3.4/16-23 0xFC0A_405E PCLRR_FBADML 0x00 16.3.4/16-23 0xFC0A_405F PCLRR_FBADL 0x00 16.3.4/16-23 16-14 Freescale Semiconductor...
Page 360 16.3.8/16-39 0xFC0A_407A DSCR_FEC 0x0F 16.3.8/16-39 0xFC0A_407B DSCR_UART 0x0F 16.3.8/16-39 0xFC0A_407C DSCR_DSPI 0x03 16.3.8/16-39 0xFC0A_407D DSCR_TIMER 0x03 16.3.8/16-39 0xFC0A_407E DSCR_SSI 0x03 16.3.8/16-39 0xFC0A_407F DSCR_DMA 0x03 16.3.8/16-39 0xFC0A_4080 DSCR_DEBUG 0x03 16.3.8/16-39 0xFC0A_4081 DSCR_RESET 0x03 16.3.8/16-39 0xFC0A_4082 DSCR_IRQ 0x03 16.3.8/16-39 Freescale Semiconductor 16-15...
Page 361: Port Output Data Registers (Podr_X)
0xFC0A_4010 (PODR_FEC1H) 0xFC0A_4011 (PODR_FEC1L) 0xFC0A_4014 (PODR_FBADH) 0xFC0A_4015 (PODR_FBADMH) 0xFC0A_4016 (PODR_FBADML) 0xFC0A_4017 (PODR_FBADL) PODR_x Reset: Figure 16-2. Port x Output Data Registers (PODR_x) Address: 0xFC0A_400A (PODR_DSPI) Access: User read/write PODR_DSPI Reset: Figure 16-3. Port DSPI Output Data Registers (PODR_DSPI) 16-16 Freescale Semiconductor...
Page 362 Figure 16-6. Port x Output Data Registers (PODR_x) Address: 0xFC0A_400F (PODR_ATAL) Access: User read/write PODR_ATAL Reset: Figure 16-7. Port ATAL Output Data Registers (PODR_ATAL) Address: 0xFC0A_4005 (PODR_CS) Access: User read/write PODR_CS Reset: Figure 16-8. Port CS Output Data Registers (PODR_CS) Freescale Semiconductor 16-17...
Page 363: Port Data Direction Registers (Pddr_X)
Address: 0xFC0A_4018 (PDDR_FEC0H) Access: User read/write 0xFC0A_4019 (PDDR_FEC0L) 0xFC0A_4021 (PDDR_UART) 0xFC0A_4024 (PDDR_PCI) 0xFC0A_4028 (PDDR_FEC1H) 0xFC0A_4029 (PDDR_FEC1L) 0xFC0A_402C (PDDR_FBADH) 0xFC0A_402D (PDDR_FBADMH) 0xFC0A_402E (PDDR_FBADML) 0xFC0A_402F (PDDR_FBADL) PDDR_x Reset: Figure 16-10. Port Data Direction Registers (PDDR_x) 16-18 Freescale Semiconductor...
Page 364 Address: 0xFC0A_401B (PDDR_FBCTL) Access: User read/write 0xFC0A_401C (PDDR_BE) 0xFC0A_401E (PDDR_DMA) 0xFC0A_4023 (PDDR_TIMER) PDDR_x Reset: Figure 16-14. Port x Output Data Registers (PDDR_x) Address: 0xFC0A_4027 (PDDR_ATAL) Access: User read/write PDDR_ATAL Reset: Figure 16-15. Port ATAL Output Data Registers (PDDR_ATAL) Freescale Semiconductor 16-19...
Page 365: Port Pin Data/Set Data Registers (Ppdsdr_X)
The PPDSDR_x registers are read/write. At reset, the bits in the PPDSDR_x registers are set to the current pin states. Reading a PPDSDR_x register returns the current state of the port x pins. Setting a PPDSDR_x register sets the corresponding bits in the PODR_x register. Writing zeroes has no effect. 16-20 Freescale Semiconductor...
Page 366 [Px4] [Px3] [Px2] [Px1] [Px0] Figure 16-20. Port x Pin Data/Set Data Registers (PPDSDR_x) Address: 0xFC0A_4032 (PPDSDR_SSI) Access: User read/write PPDR_SSI PSDR_SSI Reset: [PSSI4] [PSSI3] [PSSI2] [PSSI1] [PSSI0] Figure 16-21. Port SSI Pin Data/Set Data Registers (PPDSDR_SSI) Freescale Semiconductor 16-21...
Page 367 Figure 16-25. Port USB Pin Data/Set Data Registers (PPDSDR_USB) Table 16-7. PPDSDR_x Field Descriptions Field Description PPDR_x Port x pin data bits. (read) 0 Port x pin state is 0 1 Port x pin state is 1 16-22 Freescale Semiconductor...
Page 368: Port Clear Output Data Registers (Pclrr_X)
0xFC0A_4059 (PCLRR_FEC1L) 0xFC0A_405C (PCLRR_FBADH) 0xFC0A_405D (PCLRR_FBADMH) 0xFC0A_405E (PCLRR_FBADML) 0xFC0A_405F (PCLRR_FBADL) PCLRR_x Reset: Figure 16-26. Port x Clear Output Data Registers (PCLRR_x) Address: 0xFC0A_4052 (PCLRR_DSPI) Access: User write-only PCLRR_DSPI Reset: Figure 16-27. Port DSPI Clear Output Data Registers (PCLRR_DSPI) Freescale Semiconductor 16-23...
Page 369 Figure 16-30. Port x Clear Output Data Registers (PCLRR_x) Address: 0xFC0A_4057 (PCLRR_ATAL) Access: User write-only PCLRR_ATAL Reset: Figure 16-31. Port ATAL Clear Output Data Registers (PCLRR_ATAL) Address: 0xFC0A_404D (PCLRR_CS) Access: User write-only PCLRR_CS Reset: Figure 16-32. Port CS Clear Output Data Registers (PCLRR_CS) 16-24 Freescale Semiconductor...
Page 370: Pin Assignment Registers (Par_X)
16.3.5.1 FEC Pin Assignment Register (PAR_FEC) The PAR_FEC register controls the functions of the FEC0 and FEC1 pins. Address: 0xFC0A_4060 (PAR_FEC) Access: User read/write PAR_FEC1 PAR_FEC0 Reset: Figure 16-34. FEC Pin Assignment (PAR_FEC) Freescale Semiconductor 16-25...
Page 371 FEC0 pins configured for FEC RMII functions; MII-only pins are configured for ULPI data functions FEC0 pins configured for FEC RMII functions; MII-only pins are configured for GPIO Reserved Reserved Reserved FEC0 pins configured for FEC MII functions 16-26 Freescale Semiconductor...
Page 372 The PAR_FBCTL register controls the functions of the external FlexBus control signal pins. After reset, the FlexBus control signals are configured to their primary functions. Address: 0xFC0A_4062 (PAR_FBCTL) Access: User read/write PAR_OE PAR_TA PAR_RWB PAR_TS Reset: Figure 16-36. FlexBus Control Pin Assignment Register (PAR_FBCTL) Freescale Semiconductor 16-27...
Page 373 0 DSPI_PCS1 pin configured for GPIO 1 DSPI_PCS1 pin configured for DSPI peripheral chip select 1 function DSPI_PCS0 pin assignment. PAR_PCS0 0 DSPI_PCS0 pin configured for GPIO 1 DSPI_PCS0 pin configured for DSPI peripheral chip select 0 function 16-28 Freescale Semiconductor...
Page 374 0 FB_BE1 pin configured for GPIO 1 FB_BE1 pin configured for FlexBus byte enable 1 function Reserved, should be cleared. 3–0 FB_BE0 pin assignment. PAR_BE0 0 FB_BE0 pin configured for GPIO 1 FB_BE0 pin configured for FlexBus byte enable 0 function Freescale Semiconductor 16-29...
Page 375 Reserved, should be cleared. 16.3.5.7 Timer Pin Assignment Registers (PAR_TIMER) The PAR_TIMER register controls the functions of the DMA timer pins. Address: 0xFC0A_4066 (PAR_TIMER) Access: User read/write PAR_T3IN PAR_T2IN PAR_T1IN PAR_T0IN Reset: Figure 16-40. Timer Pin Assignment (PAR_TIMER) 16-30 Freescale Semiconductor...
Page 376 Description 7–4 Reserved, should be cleared. 3–2 USB VBUS pin assignment. Configure the USB VBUS pins for one of their primary functions or GPIO. PAR_VBUSEN 1–0 PAR_VBUSEN PAR_VBUSOC PAR_VBUSOC GPIO GPIO ULPI_NXT ULPI_STP USB_PULLUP Reserved USB_VBUS_EN USB_VBUS_OC Freescale Semiconductor 16-31...
Page 377 U0RXD pin assignment. PAR_U0RXD 0 U0RXD pin configured for GPIO 1 U0RXD pin configured for UART0 receive data function U0TXD pin assignment. PAR_U0TXD 0 U0TXD pin configured for GPIO 1 U0TXD pin configured for UART0 transmit data function 16-32 Freescale Semiconductor...
Page 378 1 FEC0_MDIO pin configured for FEC0 management data function 3–2 I2C_SCL and I2C_SDA pin assignment. These bit fields configure the I2C_SCL and I2C_SDA pins for one of their PAR_SCL primary functions or GPIO. 1–0 PAR_SDA PAR_SCL PAR_SDA GPIO GPIO U2TXD U2RXD Reserved Reserved I2C_SCL I2C_SDA Freescale Semiconductor 16-33...
Page 379 The PAR_ATA register controls the functions of the ATA pins. Address: 0xFC0A_406E (PAR_ATA) Access: User read/write PAR_ PAR_ PAR_ PAR_ PAR_ PAR_ PAR_ PAR_ PAR_ BUFEN ACS1 ACS0 ARESET DMARQ IORDY (360 TEPBGA) Reset: (256 MAPBGA) Reset Figure 16-45. ATA Pin Assignment (PAR_ATA) 16-34 Freescale Semiconductor...
Page 380 ATA_DMARQ pin assignment. PAR_DMARQ 0 ATA_DMARQ pin configured as GPIO. 1 ATA_DMARQ pin configured for ATA DMA request function. ATA_IORDY pin assignment. PAR_IORDY 0 ATA_IORDY pin configured as GPIO. 1 ATA_IORDY pin configured for ATA wait function. Freescale Semiconductor 16-35...
Page 381 REQ2 REQ1 REQ0 Reset See Note See Note Note Note Note Note Note Note Note: Reset state is 1 when the PCI is enabled through reset configuration and is 0 otherwise. Figure 16-47. PCI Pin Assignment (PAR_PCI) 16-36 Freescale Semiconductor...
Page 382 1 PCI_REQ1 pin configured for PCI request 1 function Reserved, should be cleared. PCI_REQ0 assignment. Configure the PCI_REQ0 pin for one of its primary functions or GPIO. PAR_REQ0 0 PCI_REQ0 pin configured for GPIO 1 PCI_REQ0 pin configured for PCI request 0 function Freescale Semiconductor 16-37...
Page 383: Sdram Mode Select Control Register (Mscr_Sdram)
SD_A10, SD_CAS, SD_CKE, SD_CS[1:0], SD_DQS[3:2], SD_RAS, SD_WE slew rate mode. Controls the MSCR_ strength of the SDRAM control pins. SDCTL 00 Half strength 1.8V mobile DDR 01 Full strength 1.8V mobile DDR 10 1.8V DDR2 without on-chip termination 11 2.5V DDR1 16-38 Freescale Semiconductor...
Page 384: Pci Mode Select Control Register (Mscr_Pci)
The drive strength control registers set the output pin drive strengths. All drive strength control registers are read/write. NOTE These drive strength settings are effective in all non-JTAG modes, regardless of the current functions of the pins. Freescale Semiconductor 16-39...
Page 385 Figure 16-51. FEC Drive Strength Control Register (DSCR_FEC) Address: 0xFC0A_407B (DSCR_UART) Access: User read/write DSE_UART1 DSE_UART0 Reset: Figure 16-52. UART Drive Strength Control Register (DSCR_UART) Address: 0xFC0A_4079 (DSCR_FLEXBUS) Access: User read/write DSE_FBCLK DSE_FBCTL DSE_FBADH DSE_FBADL Reset: Figure 16-53. FlexBus Drive Strength Control Register (DSCR_FLEXBUS) 16-40 Freescale Semiconductor...
Page 386 SSI_MCLK, SSI_BCLK, SSI_FS, SSI_RXD, and SSI_TXD DSCR_DMA DACK[1:0], DREQ[1:0] DSCR_DEBUG PSTDDATA[7:0] and TDO (when configured for the DSO function, JTAG_EN is negated). DSCR_RESET RSTOUT DSCR_IRQ IRQ[7,4:3] DSCR_USB USB_VBUS_EN and USB_VBUS_OC DSCR_ATA ATA_BUFFER_EN, ATA_CS[1:0], ATA_DA[2:0], ATA_RESET, ATA_DMARQ, and ATA_IORDY Freescale Semiconductor 16-41...
Page 387: Functional Description
Input Register Pin Data Figure 16-54. General Purpose Input Timing Data written to the PODR_x register of any pin configured as a general purpose output is immediately driven to its respective pin, as shown in Figure 16-55. 16-42 Freescale Semiconductor...
Page 388: Initialization/Application Information
Figure 16-55. General Purpose Output Timing 16.5 Initialization/Application Information The initialization for this module is done during reset configuration. All registers are reset to a predetermined state. Refer to Section 16.3, “Memory Map/Register Definition,” for more details on reset and initialization. Freescale Semiconductor 16-43...
Page 389 Pin Multiplexing and Control 16-44 Freescale Semiconductor...
Page 390: Introduction
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt acknowledge (IACK) cycle with the ColdFire implementation using a special memory-mapped address Freescale Semiconductor 17-1...
Page 391: Memory Map/Register Definition
Base Address INTC0 0xFC04_8000 INTC1 0xFC04_C000 Global IACK Registers Space 0xFC05_4000 This address space only contains the global SWIACK and global L1ACK-L7IACK registers. See Section 17.2.10, “Software and Level 1–7 IACK Registers (SWIACKn, L1IACKn–L7IACKn)” for more information 17-2 Freescale Semiconductor...
Page 392 Clear Interrupt Mask (CIMR1) 0x00 17.2.5/17-8 0xFC04_C040 + n Interrupt Control Registers (ICR1n) 0x00 17.2.9/17-11 (n=1:63) 0xFC04_C0E0 Software Interrupt Acknowledge (SWIACK1) 0x00 17.2.10/17-15 0xFC04_C0E0 + 4n Level n Interrupt Acknowledge Registers (LnIACK1) 0x18 17.2.10/17-15 (n=1:7) Global IACK Registers Freescale Semiconductor 17-3...
Page 393: Interrupt Pending Registers (Iprhn, Iprln)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-2. Interrupt Pending Register Low (IPRLn) 17-4 Freescale Semiconductor...
Page 394: Interrupt Mask Register (Imrhn, Imrln)
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 17-3. Interrupt Mask Register High (IMRHn) Freescale Semiconductor 17-5...
Page 395: Interrupt Force Registers (Intfrchn, Intfrcln)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-5. Interrupt Force Register High (INTFRCHn) 17-6 Freescale Semiconductor...
Page 396: Interrupt Configuration Register (Iconfig)
Only one copy of this register exists among the 2 interrupt controller modules. All reads and writes to this register must be made to the INTC0 memory space. Address: 0xFC04_801A (ICONFIG) Access: User read/write ELVLPRI EMASK Reset Figure 17-7. Interrupt Configuration Register (ICONFIG) Freescale Semiconductor 17-7...
Page 397: Set Interrupt Mask Register (Simrn)
SALL 0 Only set those bits specified in the SIMR field. 1 Set all bits in IMRn register. The SIMR field is ignored. 5–0 Set the corresponding bit in the IMRn register, masking the interrupt request. SIMR 17-8 Freescale Semiconductor...
Page 398: Clear Interrupt Mask Register (Cimrn)
In addition, an interrupt service routine can explicitly load this register with a lower priority value to query for any pending interrupts via software interrupt acknowledge cycles. Freescale Semiconductor 17-9...
Page 399: Saved Level Mask Register (Slmask)
NOTE Only one copy of this register exists among the two interrupt controller modules. All reads and writes to this register must be made to the INTC0 memory space. 17-10 Freescale Semiconductor...
Page 400: Interrupt Control Register (Icr0N, Icr1N, (N = 00, 01, 02, ..., 63))
7 interrupt is given the highest priority. If interrupt masking is enabled (ICONFIG[EMASK] = 1), the acknowledgement of a level-n request forces the controller to automatically mask all interrupt requests of level-n and lower. Freescale Semiconductor 17-11...
Page 401: Interrupt Sources
Write EDMA_CERR[CERR] = n SCMIR[CWIC] Core Watchdog Timeout Write SCMISR[CWIC] = 1 UART0 UISR0 register UART0 Interrupt Request Automatically cleared UART1 UISR1 register UART1 Interrupt Request Automatically cleared UART2 UISR2 register UART2 Interrupt Request Automatically cleared Not Used 17-12 Freescale Semiconductor...
Page 402 Heartbeat error Write EIR1[HBERR] = 1 EIR1[GRA] Graceful stop complete Write EIR1[GRA] = 1 EIR1[EBERR] Ethernet bus error Write EIR1[EBERR] = 1 EIR1[BABT] Babbling transmit error Write EIR1[BABT] = 1 EIR1[BABR] Babbling receive error Write EIR1[BABR] = 1 Freescale Semiconductor 17-13...
Page 403 Write a 1 to the necessary bit in PCIGSCR. PASR PCI arbiter interrupt Write a 1 to the necessary bit in PASR or to PACR[RA]. PSR[LOCKS] PLL loss-of-lock interrupt Wrtie a 0 to PSR[LOCKS] 58–63 Not Used 17-14 Freescale Semiconductor...
Page 404: Software And Level 1–7 Iack Registers (Swiackn, L1Iackn–L7Iackn)
Address: 0xFC04_80E0 (SWIACK0) Access: User read-only 0xFC04_80E0+4n (LnIACK0) n=1:7 0xFC04_C0E0 (SWIACK1) 0xFC04_C0E0+4n (LnIACK1) n=1:7 0xFC05_40E0 (GSWIACK) 0xFC05_40E0+4n (GLnIACK) n=1:7 VECTOR Reset (SWIACKn): Reset (LnIACKn): Figure 17-13. Software and Level n IACK Registers (SWIACKn, L1IACKn – L7IACKn) Freescale Semiconductor 17-15...
Page 405: Interrupt Controller Theory Of Operation
The level of the active request must be greater than the current mask level before it is signaled in the processor. The resulting unmasked decoded priority level is driven out of the interrupt controller. The decoded priority levels from the interrupt controllers are 17-16 Freescale Semiconductor...
Page 406 Finally, the vector number returned during the IACK cycle provides the association with the request and the physical interrupt signal. The CLMASK and SLMASK registers are all loaded (if properly enabled) during the interrupt acknowledge read cycle. Freescale Semiconductor 17-17...
Page 407: Prioritization Between Interrupt Controllers
3. The reset value for the level mask registers (CLMASK and SLMASK) is 0xF (no levels masked). Typically, these registers do not need to be modified before interrupts are enabled. 4. Load the appropriate interrupt vector tables and interrupt service routines into memory. 17-18 Freescale Semiconductor...
Page 408: Interrupt Service Routines
The bulk of the interrupt service routine executes in segment D, with interrupts enabled. Near the end of the service routine, the SR[I] field is again raised to the original acknowledged level, preparing to perform the context switch. Freescale Semiconductor 17-19...
Page 409 At the conclusion of segment G, the processor core returns to the original interrupted task or a different task ready to execute. Obviously, there are many variations to the managing of the SR[I] and the CLMASK values to create a flexible, responsive system for managing interrupt requests within the device. 17-20 Freescale Semiconductor...
Page 410: Introduction
EPDRn EPDDRn Figure 18-1. EPORT Block Diagram NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 16, “Pin Multiplexing and Control”) prior to configuring the edge-port module. Freescale Semiconductor 18-1...
Page 411: Low-Power Mode Operation
EPORT data register (EPDR). All bits in the EPDR are set at reset. 18.4 Memory Map/Register Definition This subsection describes the memory map and register structure. Refer to Table 18-2 for a description of the EPORT memory map. 18-2 Freescale Semiconductor...
Page 412: Eport Pin Assignment Register (Eppar)
EPORT Pin Assignment Register (EPPAR) The EPORT pin assignment register (EPPAR) controls the function of each pin individually. Address: 0xFC09_4000 (EPPAR) Access: Supervisor read/write EPPA7 EPPA6 EPPA5 EPPA4 EPPA3 EPPA2 EPPA1 EPPA0 Reset Figure 18-2. EPORT Pin Assignment Register (EPPAR) Freescale Semiconductor 18-3...
Page 413: Eport Data Direction Register (Epddr)
To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must be clear. Software can generate interrupt requests by programming the EPORT data register when the EPDDR selects output. 0 Corresponding EPORT pin configured as input 1 Corresponding EPORT pin configured as output 18-4 Freescale Semiconductor...
Page 414: Edge Port Interrupt Enable Register (Epier)
Reading EDPR returns the data stored in the register. Reset sets EPD7 – EPD0. 18.4.5 Edge Port Pin Data Register (EPPDR) The EPORT pin data register (EPPDR) reflects the current state of the pins. Freescale Semiconductor 18-5...
Page 415: Edge Port Flag Register (Epfr)
1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPARn = 00), pin transitions do not affect this register. 0 Selected edge for IRQn pin not detected 1 Selected edge for IRQn pin detected 18-6 Freescale Semiconductor...
Page 416: Overview
Write Address Write Data Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 19-1. eDMA Block Diagram Freescale Semiconductor 19-1...
Page 417: Features
A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that transfers these NBYTES per service request. A major loop is the number of minor loop iterations defining a task. 19-2 Freescale Semiconductor...
Page 418: Debug Mode
After a service request has been initiated, it cannot be canceled. Removing a service request after it has been asserted may result in one of three actions depending on the DMA engine’s status: • The request is never recognized because another channel is executing. Freescale Semiconductor 19-3...
Page 419: Memory Map/Register Definition
The channel priority registers assign the priorities (see Section 19.4.15, “eDMA Channel n Priority Registers (DCHPRIn)”). In round-robin arbitration mode, the channel priorities are ignored, and channels are cycled through without regard to priority. 19-4 Freescale Semiconductor...
Page 420: Edma Error Status Register (Edma_Es)
• The minor loop byte count must be a multiple of the source and destination transfer sizes. • All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. Freescale Semiconductor 19-5...
Page 421 Address: 0xFC04_4004 (EDMA_ES) Access: User read-only R VLD Reset ERRCHN Reset Figure 19-4. eDMA Error Status Register (EDMA_ES) 19-6 Freescale Semiconductor...
Page 422 0 No source bus error. 1 The last recorded error was a bus error on a source read. Destination bus error. 0 No destination bus error. 1 The last recorded error was a bus error on a destination write. Freescale Semiconductor 19-7...
Page 423: Edma Enable Request Register (Edma_Erq)
UART0 Receive UISR0[TXRDY] UART0 Transmit UISR1[FFULL/RXRDY] UART1 Receive UISR1[TXRDY] UART1 Transmit UISR2[FFULL/RXRDY] UART2 Receive UISR2[TXRDY] UART2 Transmit DTER0[CAP] or DTER0[REF] / Timer 0 / SSI0 Receive SSISR[RFF0] DTER1[CAP] or DTER1[REF] / Timer 1 / SSI1 Receive SSISR[RFF1] 19-8 Freescale Semiconductor...
Page 424: Edma Enable Error Interrupt Registers (Edma_Eei)
Table 19-7. EDMA_EEI Field Descriptions Field Description 15–0 Enable error interrupt n. EEIn 0 The error signal for channel n does not generate an error interrupt. 1 The assertion of the error signal for channel n generates an error interrupt request. Freescale Semiconductor 19-9...
Page 425: Edma Set Enable Request Register (Edma_Serq)
EDMA_ERQ to be cleared, disabling all DMA request inputs. Reads of this register return all zeroes. Address: 0xFC04_4019 (EDMA_CERQ) Access: User write-only CAER CERQ Reset Figure 19-8. eDMA Clear Enable Request Register (EDMA_CERQ) 19-10 Freescale Semiconductor...
Page 426: Edma Set Enable Error Interrupt Register (Edma_Seei)
The data value on a register write causes the corresponding bit in the EDMA_EEI to be cleared. Setting the CAEE bit provides a global clear function, forcing the EDMA_EEI contents to be cleared, disabling all DMA request inputs. Reads of this register return all zeroes. Freescale Semiconductor 19-11...
Page 427: Edma Clear Interrupt Request Register (Edma_Cint)
Figure 19-11. eDMA Clear Interrupt Request (EDMA_CINT) Table 19-12. EDMA_CINT Field Descriptions Field Description Reserved, must be cleared. Clear all interrupt requests. CAIR 0 Clear only those EDMA_INT bits specified in the CINT field. 1 Clear all bits in EDMA_INT. 19-12 Freescale Semiconductor...
Page 428: Edma Clear Error Register (Edma_Cerr)
The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. Reads of this register return all zeroes. Freescale Semiconductor 19-13...
Page 429: Edma Clear Done Status Bit Register (Edma_Cdne)
Clears all DONE bits. CADN 0 Clears only those TCDn_CSR[DONE] bits specified in the CDNE field. 1 Clears all bits in TCDn_CSR[DONE] 5–4 Reserved, must be cleared. 3–0 Clear DONE bit. Clears the corresponding bit in TCDn_CSR[DONE]. CDNE 19-14 Freescale Semiconductor...
Page 430: Edma Interrupt Request Register (Edma_Int)
A zero in any bit position has no affect on the corresponding channel’s current error status. The EDMA_CERR is provided so the error indicator for a single channel can easily be cleared. Freescale Semiconductor 19-15...
Page 431: Edma Channel N Priority Registers (Dchprin)
CHPRI Reset – – – – Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111. Figure 19-17. eDMA Channel n Priority Register (DCHPRIn) 19-16 Freescale Semiconductor...
Page 432: Transfer Control Descriptors (Tcdn)
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 19-18. TCDn Source Address (TCDn_SADDR) Freescale Semiconductor 19-17...
Page 433 Destination data transfer size. See the SSIZE definition. DSIZE Address: 0xFC04_5006 + (0x20 n) (TCDn_SOFF) Access: User read/write SOFF Reset — — — — — — — — — — — — — — — — Figure 19-20. TCDn Signed Source Address Offset (TCDn_SOFF) 19-18 Freescale Semiconductor...
Page 434 Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 19-23. TCDn Destination Address (TCDn_DADDR) Freescale Semiconductor 19-19...
Page 435 Note: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 19-20 Freescale Semiconductor...
Page 436 Access: User read/write E_LINK = 1 E_LINK LINKCH BITER E_LINK = 0 E_LINK BITER Reset — — — — — — — — — — — — — — — — Figure 19-27. TCDn Beginning Major Iteration Count (TCDn_BITER) Freescale Semiconductor 19-21...
Page 437 Address: 0xFC04_501E + (0x20 n) (TCDn_CSR) Access: User read/write MAJOR_ INT_ INT_ MAJOR_LINKCH DONE ACTIVE E_SG D_REQ START E_LINK HALF MAJOR Reset — — — — — — — — — — — — — Figure 19-28. TCDn Control and Status (TCDn_CSR) 19-22 Freescale Semiconductor...
Page 438 Disable request. If this flag is set, the eDMA hardware automatically clears the corresponding EDMA_ERQ D_REQ bit when the current major iteration count reaches zero. 0 The channel’s EDMA_ERQ bit is not affected. 1 The channel’s EDMA_ERQ bit is cleared when the major loop is complete. Freescale Semiconductor 19-23...
Page 439: Functional Description
If the major iteration count is exhausted, additional processing are performed, including the final address pointer updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation. 19-24 Freescale Semiconductor...
Page 440: Edma Basic Data Flow
The TCD memory is 64 bits wide to minimize the time needed to fetch the activated channel descriptor and load it into the address path channel x or y registers. Freescale Semiconductor 19-25...
Page 441 The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write. This source read/destination write processing continues until the minor byte count has transferred. 19-26 Freescale Semiconductor...
Page 442 TCD from memory using the scatter/gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 19-31. Freescale Semiconductor 19-27...
Page 443: Initialization/Application Information
4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the EDMA_ERQ. 6. Request channel service by software (setting the TCDn_CSR[START] bit) or hardware (slave device asserting its eDMA peripheral request signal). 19-28 Freescale Semiconductor...
Page 444 DMA request initiates one minor-loop transfer (iteration) without CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). Freescale Semiconductor 19-29...
Page 445 Table 19-32. Example of Multiple Loop Iterations Current Major Loop Iteration Count (CITER) DMA Request Minor Loop DMA Request Minor Loop Major Loop DMA Request Minor Loop Table 19-33 lists the memory array terms and how the TCD settings interrelate. 19-30 Freescale Semiconductor...
Page 446: Dma Programming Errors
19.6.3 DMA Arbitration Mode Considerations 19.6.3.1 Fixed Channel Arbitration In this mode, the channel service request from the highest priority channel is selected to execute. Freescale Semiconductor 19-31...
Page 447: Dma Transfer
4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source-to-destination transfers are executed as follows: a) Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. 19-32 Freescale Semiconductor...
Page 448 Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d) Write longword to location 0x2004  second iteration of the minor loop. e) Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. Freescale Semiconductor 19-33...
Page 449 Table 19-34 shows how the transfer addresses are specified based on the setting of the MOD field. Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits 19-34 Freescale Semiconductor...
Page 450: Edma Tcdn Status Monitoring
TCDn_CITER field and test for a change. The hardware request and acknowledge handshakes signals are not visible in the programmer’s model. The TCD status bits execute the following sequence for a hardware-activated channel: Freescale Semiconductor 19-35...
Page 451: Channel Linking
The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop). The TCDn_CITER[E_LINK] field determines whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the major loop except for the last. When the major 19-36 Freescale Semiconductor...
Page 452: Dynamic Programming
This section provides recommended methods to change the programming model during channel execution. 19.6.7.1 Dynamic Channel Linking and Dynamic Scatter/Gather Dynamic channel linking and dynamic scatter/gather is the process of changing the TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits during channel execution. These bits are read Freescale Semiconductor 19-37...
Page 453 TCDn after the TCDn_CSR[DONE] bit for that channel is set, indicating the major loop is complete. NOTE Software must clear the TCDn_CSR[DONE] bit before writing the TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits. The TCDn_CSR[DONE] bit is cleared automatically by the eDMA engine after a channel begins execution. 19-38 Freescale Semiconductor...
Page 454: Introduction
• Six independent, user-programmable chip-select signals (FB_CS[5:0]) that can interface with external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals • 8-, 16-, and 32-bit port sizes with configuration for multiplexed or non-multiplexed address and data buses Freescale Semiconductor 20-1...
Page 455: External Signals
See Table 1-1Table 2-2 for more details. FB_BE/BWE[3:0] Byte enable/byte write enable FB_OE Output enable FB_R/W Read/write. 1 = Read, 0 = Write FB_ALE Address latch enable FB_TSIZ[1:0] Transfer size FB_TBST Burst transfer indicator FB_TA Transfer acknowledge 20-2 Freescale Semiconductor...
Page 456: Address And Data Buses (Fb_An, Fb_Dn, Fb_Adn)
Output Enable (FB_OE) The output enable signal (FB_OE) is sent to the interfacing memory and/or peripheral to enable a read transfer. FB_OE is only asserted during read accesses when a chip select matches the current address decode. Freescale Semiconductor 20-3...
Page 457: Read/Write (Fb_R/W)
For burst-inhibited transfers, FB_TSIZ[1:0] changes with each FB_TS assertion to reflect the next transfer size. For transfers to port sizes smaller than the transfer size, FB_TSIZ[1:0] indicates the size of the entire transfer on the first access and the size of the current port transfer on subsequent transfers. For example, 20-4 Freescale Semiconductor...
Page 458: Transfer Burst (Fb_Tbst)
NOTE You must set CSMR0[V] before the chip select registers take effect. Freescale Semiconductor 20-5...
Page 459: Chip-Select Address Registers (Csar0 – Csar5)
31–16 Base address. Defines the base address for memory dedicated to chip-select FB_CSn. BA is compared to bits 31–16 on the internal address bus to determine if chip-select memory is being accessed. 15–0 Reserved, must be cleared. 20-6 Freescale Semiconductor...
Page 460: Chip-Select Mask Registers (Csmr0 – Csmr5)
Chip-Select Control Registers (CSCR0 – CSCR5) Each CSCRn controls the auto-acknowledge, address setup and hold times, port size, burst capability, and number of wait states. To support the global chip-select, FB_CS0, the CSCR0 reset values differ from the Freescale Semiconductor 20-7...
Page 461 01 Assert FB_CSn on second rising clock edge after address is asserted. 10 Assert FB_CSn on third rising clock edge after address is asserted. 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) 20-8 Freescale Semiconductor...
Page 462 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] 1x 16-bit port size. Valid data sampled and driven on FB_D[31:16] Freescale Semiconductor 20-9...
Page 463: Functional Description
Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, address setup and hold times, and automatic acknowledge generation features. See Section 20.3.3, “Chip-Select Control Registers (CSCR0 – CSCR5).” FB_CS0 is a global chip-select after reset and provides external boot memory capability. 20-10 Freescale Semiconductor...
Page 464: Data Transfer Operation
During serial boot, the value of SBF_RCON[127:126] determine the port size. Chapter 11, “Chip Configuration Module (CCM),” for more information. 20.4.2 Data Transfer Operation Data transfers between the chip and other devices involve these signals: • Address/data bus (FB_AD[31:0]) Freescale Semiconductor 20-11...
Page 465: Data Byte Alignment And Physical Connections
-bit address is always driven on the first clock of a bus cycle. During the data phase, the FB_AD[ lines used for data are determined by the programmed port size for the corresponding chip select. The device continues to drive the address on any FB_AD[ :0] lines not used for data. 20-12 Freescale Semiconductor...
Page 466: Bus Cycle Execution
4. S3: FB_CSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes, and write data. Freescale Semiconductor 20-13...
Page 467: Data Transfer Cycle States
Address, data, and FB_R/W go invalid off the rising edge of FB_CLK at the beginning of S3, terminating the read or write cycle. 20.4.6 FlexBus Timing Examples NOTE Because this device shares the FlexBus signals with the PCI controller, all signals, except the chip selects, tristate between bus cycles. 20-14 Freescale Semiconductor...
Page 468: Basic Read Bus Cycle
However, some applications may find this beneficial. The address and data busses are muxed between the FlexBus and PCI controller. At the end of the read bus cycles the address signals are indeterminate. Freescale Semiconductor 20-15...
Page 469: Basic Write Bus Cycle
1. Select the appropriate slave device. FlexBus asserts internal FB_TA (auto acknowledge/internal termination). 2. Latch data on FB_AD[31:X]. Sample FB_TA low. Assert FB_TA (external termination). 1. Negate FB_TA (external termination). 1. Start next cycle. Figure 20-8. Write-Cycle Flowchart 20-16 Freescale Semiconductor...
Page 470 8-bit device with no wait states. The address is driven on the full FB_AD[ 31:8 ] bus in the first clock. The device tristates FB_AD[ 31:24] on the second clock and continues to drive address on Freescale Semiconductor 20-17...
Page 471 The data is driven from the second clock on FB_AD[31:24]. FB_CLK ADDR[23:0] FB_AD[23:0] Mux’d Bus FB_AD[31:24] ADDR[31:24] DATA[7:0] FB_A[23:0] ADDR[23:0] Non-Mux’d Bus FB_D[31:24] ADDR[31:24] DATA[7:0] FB_R/W FB_ALE FB_CSn, FB_BE/BWEn FB_OE FB_TA FB_TSIZ[1:0] Figure 20-11. Single Byte-Write Transfer 20-18 Freescale Semiconductor...
Page 472 FB_AD[31:16], and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted. FB_CLK FB_AD[15:0] ADDR[15:0] Mux’d Bus FB_AD[31:16] ADDR[31:16] DATA[15:0] FB_A[23:0] ADDR[23:0] Non-Mux’d Bus FB_D[31:16] ADDR[31:16] DATA[15:0] FB_R/W FB_ALE FB_CSn, FB_BE/BWEn FB_OE FB_TA FB_TSIZ[1:0] Figure 20-12. Single Word-Read Transfer Freescale Semiconductor 20-19...
Page 473 Figure 20-13. Single Word-Write Transfer Figure 20-14 depicts a longword read from a 32-bit device. FB_CLK Mux’d Bus ADDR[31:0] FB_AD[31:0] DATA[31:0] FB_A[23:0] ADDR[23:0] Non-Mux’d Bus ADDR[31:0] FB_D[31:0] DATA[31:0] FB_R/W FB_ALE FB_CSn, FB_OE FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 20-14. Longword-Read Transfer 20-20 Freescale Semiconductor...
Page 474: Timing Variations
20.4.6.4.1 Wait States Wait states can be inserted before each beat of a transfer by programming the CSCRn registers. Wait states can give the peripheral or memory more time to return read data or sample write data. Freescale Semiconductor 20-21...
Page 475 Figure 20-16. Basic Read-Bus Cycle (No Wait States) FB_CLK FB_AD[Y:0] ADDR[Y:0] Mux’d Bus FB_AD[31:X] ADDR[31:X] DATA FB_A[23:0] ADDR[23:0] Non-Mux’d Bus FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_ALE FB_CSn, FB_BE/BWEn FB_OE FB_TA FB_TSIZ[1:0] TSIZ[1:0] Figure 20-17. Basic Write-Bus Cycle (No Wait States) 20-22 Freescale Semiconductor...
Page 476 Figure 20-18. Read-Bus Cycle (One Wait State) FB_CLK FB_AD[Y:0] ADDR[Y:0] Mux’d Bus FB_AD[31:X] ADDR[31:X] DATA FB_A[23:0] ADDR[23:0] Non-Mux’d Bus FB_D[31:X] ADDR[31:X] DATA DATA FB_R/W FB_ALE FB_CSn, FB_BE/BWEn FB_OE FB_TA FB_TSIZ[1:0] TSIZ[1:0] Figure 20-19. Write-Bus Cycle (One Wait State) Freescale Semiconductor 20-23...
Page 477 Figure 20-20. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) FB_CLK FB_AD[Y:0] ADDR[Y:0] Mux’d Bus FB_AD[31:X] DATA ADDR[31:X] FB_A[23:0] ADDR[23:0] Non-Mux’d Bus FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_ALE FB_CSn, FB_BE/BWEn FB_OE FB_TA TSIZ[1:0] FB_TSIZ[1:0] Figure 20-21. Write-Bus Cycle with Two Clock Address Setup (No Wait States) 20-24 Freescale Semiconductor...
Page 478 Figure 20-22. Read Cycle with Two-Clock Address Hold (No Wait States) FB_CLK FB_AD[Y:0] ADDR[Y:0] Mux’d Bus FB_AD[31:X] ADDR[31:X] DATA FB_A[23:0] ADDR[23:0] Non-Mux’d Bus FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_ALE FB_CSn, FB_BE/BWEn FB_OE FB_TA FB_TSIZ[1:0] TSIZ[1:0] Figure 20-23. Write Cycle with Two-Clock Address Hold (No Wait States) Freescale Semiconductor 20-25...
Page 479: Burst Cycles
Table 20-11. Transfer Size and Port Size Translation Transfer Size Burst-Inhibited: Number of Transfers Port Size PS[1:0] FB_TSIZ[1:0] Burst Enabled: Number of Beats 01 (8-bit) 10 (word) 00 (longword) 11 (line) 1x (16-bit) 00 (longword) 11 (line) 00 (32-bit) 11 (line) 20-26 Freescale Semiconductor...
Page 480 The first beat of any write burst cycle has at least one wait state. If the bus cycle is programmed for zero wait states (CSCRn[WS] = 0), one wait state is added. Otherwise, the programmed number of wait states are used. Freescale Semiconductor 20-27...
Page 481 The transfer size is driven at longword (00) during the first transfer and at byte (01) during the next three transfers. NOTE There is an extra clock of address setup (AS) for each burst-inhibited transfer between states S0 and S1. 20-28 Freescale Semiconductor...
Page 482 ADDR + 1 ADDR + 2 ADDR + 3 ADDR FB_D[31:24] DATA DATA DATA DATA DATA [31:24] FB_R/W FB_ALE FB_CSn, FB_OE, FB_BE/BWEn FB_TBST FB_TA FB_TSIZ[1:0] 01 01 Figure 20-27. Longword-Read Burst-Inhibited from 8-Bit Port (No Wait States) Freescale Semiconductor 20-29...
Page 483 NOTE CSCRn[WS] determines the number of wait states in the first beat. However, for subsequent beats, the CSCRn[WS] (or CSCRn[SWS] if CSCRn[SWSEN] is set) determines the number of wait states. 20-30 Freescale Semiconductor...
Page 484 FB_A[23:0] ADDR[23:0] ADDR + 1 ADDR + 2 ADDR + 3 ADDR FB_D[31:24] DATA DATA DATA DATA [31:24] FB_R/W FB_ALE FB_CSn, FB_OE, FB_BE/BWEn, FB_TBST FB_TA FB_TSIZ[1:0] Figure 20-30. Longword-Write Burst to 8-Bit Port 3-2-2-2 (One Wait State) Freescale Semiconductor 20-31...
Page 485 FB_BE/BWEn, FB_TBST FB_TA FB_TSIZ[1:0] The address hold time depends on the setting of CSCRn[AA]. See Section 20.3.3, “Chip-Select Control Registers (CSCR0 – CSCR5)”, for more details. Figure 20-31. Longword-Read Burst from 8-Bit Port 3-1-1-1 (Address Setup and Hold) 20-32 Freescale Semiconductor...
Page 486 FB_A[23:0] ADDR[23:0] ADDR + 1 ADDR + 2 ADDR + 3 FB_D[31:24] ADDR[31:24] DATA DATA DATA DATA FB_R/W FB_ALE FB_CSn, FB_OE, FB_BE/BWEn, FB_TBST FB_TA FB_TSIZ[1:0] Figure 20-32. Longword-Write Burst to 8-Bit Port 3-1-1-1 (Address Setup and Hold) Freescale Semiconductor 20-33...
Page 487: Misaligned Operands
FB_TA. If the processor must manage a bus error differently, asserting an interrupt to the core along with FB_TA when the bus error occurs can invoke an interrupt handler. The device also includes a bus monitor that generates a bus error for unterminated cycles. 20-34 Freescale Semiconductor...
Page 488: Introduction
It also includes examples to better understand how to configure the DRAM controller for synchronous operations. NOTE Unless otherwise noted, in this chapter clock refers to the system clock sys/2 Freescale Semiconductor 21-1...
Page 489: Block Diagram
The maximum row bits plus column bits equals 25 in 16-bit bus mode. • Minimum memory configuration of 8 MByte — 11 bit row address (RA), 9 bit column address (CA), 2 bit bank address (BA), 16-bit bus, one chip select 21-2 Freescale Semiconductor...
Page 490: Terminology
O Memory bank address. Define which bank an , or PRECHARGE command is being ACTV READ WRITE applied. It is also used to select the SDRAM internal mode register during power-up initialization. Timing Assertion/Negation — Occurs synchronously with SD_CLK Freescale Semiconductor 21-3...
Page 491 O Output mask signal for write data. During reads, SD_DQM may be driven high, low, or floating. The address correspondence: SD_DQM3 - SD_D[31:24] SD_DQM2 - SD_D[23:16] State Asserted — Data is written to SDRAM Meaning Negation — Data is masked Timing Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK. 21-4 Freescale Semiconductor...
Page 492: Interface Recommendations
(RA, CA, and BA respectfully). IA[9:1] are used for CA[8:0]. IA[11:10] are used for BA[1:0], and IA[23:12] are used for RA[11:0]. IA[27:24] can be used for additional row or column address bits, as needed. The additional row- or column-address bits are programmed via the SDCR[ADDR_MUX] bits. Freescale Semiconductor 21-5...
Page 493 14 x 9 x 4 — — RA13 RA12 12 x 12 x 4 — CA12 CA11 64M x 4 bit 13 x 11 x 4 — CA11 RA12 14 x 10 x 4 — RA13 RA12 21-6 Freescale Semiconductor...
Page 494 If all devices’ column address width is 9 bits, the row address can be  11 bits. • • The maximum row bits plus column bits equals 25. • x16 data width memory devices cannot be mixed with any other width. Freescale Semiconductor 21-7...
Page 495: Sdram Ddr Component Connections
Use a VREF plane under the SDRAM. • VREF is decoupled from SDVDD and VSS. • To avoid crosstalk, address and command signals must remain separate from data and data strobes. • Use different resistor packs for command/address and data/data strobes. 21-8 Freescale Semiconductor...
Page 496: Termination Example
SDRAM controller control and configuration registers. Unspecified memory spaces are reserved for future use. Access to reserved space is prohibited. It is recommended to write 0 to reserved space. Reads from a write-only bit return 0. Freescale Semiconductor 21-9...
Page 497: Sdram Mode/Extended Mode Register (Sdmr)
Address for DDR2 SDRAMs. Driven onto SD_A[13:0] along with an command. The AD value is stored as LEMR DDR2_AD the mode (or extended mode) register data. Note: SDCR[DDR_MODE, DDR2_MODE] must be set for this value to appear on the bus. 21-10 Freescale Semiconductor...
Page 498: Sdram Control Register (Sdcr)
When not being driven for a write cycle, SD_D hold the most recent value and SD_DQS are driven low. This mode is intended for minimal applications only, to prevent floating signals and allow unterminated board traces. However, terminated wiring is always recommended over unterminated. Freescale Semiconductor 21-11...
Page 499: Sdram Configuration Register 1 (Sdcfg1)
The 32-bit read/write SDRAM configuration register 1 (SDCFG1) stores necessary delay values between specific SDRAM commands. During initialization, software loads values to the register according to the selected SD_CLK frequency and SDRAM information obtained from the data sheet. This register resets only by a power-up reset signal. 21-12 Freescale Semiconductor...
Page 500 BurstLength/2 + AL; If AL (additive latency) is less than 2, then use 2. is the time the data bus uses to return to hi-impedance after a read and is found in the SDRAM device specifications. Note: Count value is in SD_CLK periods for DDR mode. Reserved, must be cleared. Freescale Semiconductor 21-13...
Page 501 If t = 75ns and f = 99 MHz SD_CLK Suggested value = (75ns  99 MHz) - 1 = 6.425; round to 7. Note: Count value is in SD_CLK periods for DDR1/2 modes. Reserved, must be cleared. 21-14 Freescale Semiconductor...
Page 502: Sdram Configuration Register 2 (Sdcfg2)
DDR2: BRD2W = BurstLength/2 + 2. Suggested value = 0x6. 19–16 Burst length. BL = BurstLength - 1 Note: Burst length depends on port size. If 16-bit bus (SDCR[MEM_PS] = 1), burst length is 8. Write BL = 7. 15–0 Reserved, must be cleared. Freescale Semiconductor 21-15...
Page 503: Sdram Chip Select Configuration Registers (Sdcsn)
Chip-select base address. Because the SDRAM module is one of the slaves connected to the crossbar switch, it is CSBA only accessible within a certain memory range. The only applicable address ranges for which the chip-selects can be active are 0x4000_0000 – 0x7FFF_FFFF. Therefore, the possible range for this field is 0x400 – 0x7FF. 21-16 Freescale Semiconductor...
Page 504: Sdram Commands
When an internal bus master accesses SDRAM address space, the memory controller generates the corresponding SDRAM command. Table 21-10 lists SDRAM commands supported by the memory controller. Table 21-10. SDRAM Commands Function Symbol BA[1:0] A[10] Other A Command Inhibit No Operation Freescale Semiconductor 21-17...
Page 505 Then, the SDRAMC issues ACTV to activate the necessary row and bank for the new access, followed by the read to the SDRAM. 21-18 Freescale Semiconductor...
Page 506 Refresh interval elapsed • Software commanded precharge during device initialization NOTE A precharge is required after DRAMs also have a maximum bank-open period. The memory controller does not time the bank-open period because the refresh interval is always less. Freescale Semiconductor 21-19...
Page 507 00000 Normal Operation 00010 Reset DLL Else Reserved A6–A4 CAS latency. Delay in clocks from issuing a to valid data out. Check the SDRAM manufacturer’s spec because READ the CL settings supported can vary from memory to memory. 21-20 Freescale Semiconductor...
Page 508 SDRAM’s extended mode register, not the SDRAMC’s mode/extended-mode register (SDMR) defined in Section 21.4.1, “SDRAM Mode/Extended Mode Register (SDMR).” Refer to the SDRAM manufacturer’s device data sheet to confirm correct settings. Field — TCSR PASR Figure 21-11. Typical Mobile DDR Extended Mode Register Freescale Semiconductor 21-21...
Page 509 (WR[cycles] = t (ns)/t (ns)). The mode register must be programmed to this value. This is also used with t to determine t 000 Reserved 001 2 010 3 011 4 100 5 101 6 11x Reserved 21-22 Freescale Semiconductor...
Page 510 RDQS enable. If RDQS is enabled, DM function is disabled. RDQS is active for reads and don’t care for RDQS writes. Used in conjunction with DQS to produce the strobe function matrix in Table 21-16. 0 Disable 1 Enable. DQS enable. Enables the DQS signals to be used for data strobes. 0 Enable 1 Disable Freescale Semiconductor 21-23...
Page 511 2 and 3 used by DDR2 SDRAMs. This is the SDRAM’s extended mode register, and not the SDRAMC’s mode/extended mode register (SDMR) described in Section 21.4.1, “SDRAM Mode/Extended Mode Register (SDMR)”. Field Figure 21-14. DDR2 Extended Mode Register 2 21-24 Freescale Semiconductor...
Page 512 CKE; this would put the memory in power down mode. To restart periodic refresh when the memory reactivates, the REF_EN bit must be reasserted; this can be done before the memory reactivates or in the same control register write that sets CKE to exit self-refresh mode. Freescale Semiconductor 21-25...
Page 513: Read Clock Recovery (Rcr) Block
DQS edges to achieve data-center alignment instead of data-edge alignment. There are two data valid windows per memory clock period with DDR, so the nominal delay of read clocks from DQS is 1/4 memory clock period. 21-26 Freescale Semiconductor...
Page 514: Initialization/Application Information
(usually two). Write to the SDCR with the IREF and MODE_EN bits set (SDCR[REF and IPALL] must be cleared). This forces a refresh of the SDRAM each time the IREF bit is set. Repeat this step until the specified number of refresh cycles have been completed. Freescale Semiconductor 21-27...
Page 515: Low-Power/Mobile Sdram Initialization Sequence
2. Configure pin multiplex control for shared SD_CS pins in pin multiplexing and control module if needed. 3. Configure the slew rate for the SDRAM external pins in the pin multiplexing and control module’s MSCR_SDRAM register if needed. 4. Write the SDCSn register values for each chip select that is used. 21-28 Freescale Semiconductor...
Page 516: Page Management
(number of contiguous columns per bank)  (number of bits). This gives a contiguous page size of 1 KBytes. However, the total (possibly fragmented) page size is (number of banks)  (number of columns)  (number of bits). Freescale Semiconductor 21-29...
Page 517: Transfer Size
2 bytes (16-bit mode) on the memory bus. The SDRAM controller follows the critical beat first, sequential transfer format required. The burst size and transfer order must be programmed in the SDRAM mode registers during initialization; the burst size also must be programmed in the memory controller (SDCFG2 register). 21-30 Freescale Semiconductor...
Page 518: Introduction
Target Target Interface Master Bus Initiator Initiator Interface Figure 22-1. PCI Block Diagram 22.1.2 Overview The peripheral component interface (PCI) bus is a high-performance bus with multiplexed address and data lines, especially suitable for high data-rate applications. Freescale Semiconductor 22-1...
Page 519: Features
The internal PCI arbiter can be statically configured as enabled or disabled. When disabled, an external arbiter is responsible for PCI arbitration and the PCI controller’s request and grant signals are presented as external pins of the device. 22-2 Freescale Semiconductor...
Page 520: External Signal Description
Section 22.4.6, “PCI Clock Scheme.” 22.2.3 Command/Byte Enables (PCI_CBE[3:0]) The PCI_CBE[3:0] signals are time multiplexed. The PCI command is presented during the address phase and the byte enables are presented during the data phase. Byte enables are active low. Freescale Semiconductor 22-3...
Page 521: Device Select (Pci_Devsel)
The PCI_REQ[3:0] signals assert by external PCI masters when they require access to the PCI bus. When the internal PCI arbiter module is disabled, PCI_REQ[0] is the grant input for the PCI controller. It is driven by an external PCI arbiter. 22-4 Freescale Semiconductor...
Page 522: Reset (Pci_Rst)
0xFC0A_8000 PCI Device ID/Vendor ID (PCIIDR) 0x5807_1957 22.3.1.1/22-7 0xFC0A_8004 PCI Status/Command (PCISCR) 0x02A0_0000 22.3.1.2/22-8 0xFC0A_8008 PCI Class Code/Revision ID (PCICCRIR) 0x0680_0000 22.3.1.3/22-10 0xFC0A_800C PCI Configuration 1 Register (PCICR1) 0x0000_0000 22.3.1.4/22-10 0xFC0A_8010 PCI Base Address Register 0 (PCIBAR0) 0x0000_0000 22.3.1.5/22-11 Freescale Semiconductor 22-5...
Page 523 0xFC0A_8094 PCI Target Base Address Translation Register 1 0x0000_0000 22.3.2.10/22-23 (PCITBATR1) 0xFC0A_8098 PCI Target Base Address Translation Register 2 0x0000_0000 22.3.2.10/22-23 (PCITBATR2) 0xFC0A_809C PCI Target Base Address Translation Register 3 0x0000_0000 22.3.2.10/22-23 (PCITBATR3) 0xFC0A_80A0 PCI Target Base Address Translation Register 4 0x0000_0000 22.3.2.10/22-23 (PCITBATR4) 22-6 Freescale Semiconductor...
Page 524: Pci Type 0 Configuration Registers
This field is read-only and represents the PCI Device ID assigned to this processor. Its value is: 0x5807. Device ID 15–0 This field is read-only and represents the PCI Vendor ID assigned to this processor. Its value is: 0x1957. Vendor ID Freescale Semiconductor 22-7...
Page 525 A PCI configuration cycle writing a 1 to the bit clears it. Writing 0 has no effect. Fast back-to-back capable. Fixed to 1. This read-only bit indicates that the PCI controller as target is capable of accepting fast back-to-back transactions with other targets. 22-8 Freescale Semiconductor...
Page 526 I/O access control. Fixed to 0. This bit is not implemented because there is no PCI controller I/O type space accessible from the PCI bus. The PCI base address registers are memory address ranges only. Initialization software must write a 0 to this bit location. Freescale Semiconductor 22-9...
Page 527 Latency timer [2:0] The lower three bits of the bit field are hardwired low. 7–0 Cache line size[7:4] Specifies the cache line size in units of DWORDs. The higher four bits of the bit field are hardwired low Cache line size[3:0] Specifies the cache line size in units of DWORDs. 22-10 Freescale Semiconductor...
Page 528 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREF RANGE IO/M# BAR4 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-10. PCIBAR4 Register Freescale Semiconductor 22-11...
Page 529 This optional register contains the pointer to the card information structure (CIS) for the CardBus card. All 32 bits of the register are programmable by the slave bus. This register can only be read from the PCI bus, not written. 22-12 Freescale Semiconductor...
Page 530 Indicates the manufacturer identification number of the add-in board or subsystem containing this PCI device. Subsystem Vendor ID 22.3.1.8 Expansion ROM Base Address (PCIERBAR)—PCI Dword C Not implemented. Fixed to 0x0000_0000 at address 0xFC0A_8030. 22.3.1.9 Capabilities Pointer (Cap_Ptr) (PCICPR)—PCI Dword D Not implemented. Fixed to 0x0000_0000 at address 0xFC0A_8034. Freescale Semiconductor 22-13...
Page 531: General Control/Status Registers
DMA interface. These registers are accessed primarily internally, but can also be accessed by an external PCI master if PCI base and target base address registers are configured to access the space. See Section 22.5.2, “Address Translation,” configuring address windows. 22-14 Freescale Semiconductor...
Page 532 PLL settings, PCI controller could malfunction. 000 Reserved 001 Divide by 1 010 Divide by 2 011 Divide by 3 100 Divide by 4 101 Divide by 5 110 Divide by 1.5 (Multiply by 111 Reserved 23–19 Reserved, must be cleared. Freescale Semiconductor 22-15...
Page 533 The next two registers, PCITBATR0 and PCITBATR1, are aliases for the registers at address 0xFC0A_8090 and 0xFC0A_8094 respectively. When these registers are written to, it also updates the contents of the other PCITBATR0 and PCITBATR1 registers. Likewise, when PCITBATR0 at address 22-16 Freescale Semiconductor...
Page 534 19–1 Reserved, must be cleared. Enable 1. Enables a transaction in BAR1 space. If this bit is zero and a hit on PCI address space indicated by BAR1 occurs, the target interface gasket aborts the PCI transaction. Freescale Semiconductor 22-17...
Page 535 The reset value of the write combine timer is 0x08. All 8 bits are programmable. 22.3.2.5 Initiator Window n Base/Translation Address Register (PCIIWnBTAR) The following register figure describes the three initiator window base/translation address registers. 22-18 Freescale Semiconductor...
Page 536 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-20. PCIIWCR Register Freescale Semiconductor 22-19...
Page 537 REE IAE TAE Maximum Retries Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Figure 22-22. PCIICR Register 22-20 Freescale Semiconductor...
Page 538 This indicates no target responded by asserting PCI_DEVSEL within the time allowed for subtractive decoding. A CPU interrupt generates if the PCIICR[IAE] bit is set. Application software must write a 1 to it clears this bit. Freescale Semiconductor 22-21...
Page 539 If low (agent mode), the bit is 1 out of reset, forcing configuration accesses to retry until initialization software clears this bit. Note: For normal target operation, this bit must be cleared. After cleared, this bit must not be set again unless resetting the PCI system. 22-22 Freescale Semiconductor...
Page 540 BAT5 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-30. PCITBATR5 Register Freescale Semiconductor 22-23...
Page 541 When this bit is cleared, PCI_INTA is negated. Software must program this bit high when PCI_INTA assertion is desired. The reset value of the bit is 0 (PCI_INTA not asserted). Note: External PCI_INTA pin specifies asserted when low and is an open-drain signal (high impedance when negated). 22-24 Freescale Semiconductor...
Page 542: Pci Arbiter Registers
DWord address offset. Selects the Dword address offset in the configuration space of the target device. DWORD 1–0 Reserved, must be cleared. 22.3.3 PCI Arbiter Registers The PCI arbiter provides contains two registers accessed by 8-bit, 16-bit, or 32-bit accesses. Freescale Semiconductor 22-25...
Page 543 When this bit subsequently clears, requests from broken masters are once again recognized and arbitration resumes. This reset bit does not prohibit register access, but it must be cleared for arbitration to occur. When set, the arbiter parks with the internal master. 14–5 Reserved, must be cleared. 22-26 Freescale Semiconductor...
Page 544: Functional Description
PCI arbiter or off-chip. (See Section 22.4.5, “PCI Arbiter”). The registers, described in Section 22.3, “Memory Map/Register Definition,” control and provide information about multiple interfaces. An additional configuration interface allows internal access through Freescale Semiconductor 22-27...
Page 545: Pci Bus Protocol
0100 Reserved 0101 Reserved 0110 MEMORY READ 0111 MEMORY WRITE 1000 Reserved 1001 Reserved 1010 CONFIGURATION READ 1011 CONFIGURATION WRITE 1100 MEMORY READ MULTIPLE 1101 DUAL ADDRESS CYCLE 1110 MEMORY READ LINE 1111 MEMORY WRITE AND INVALIDATE 22-28 Freescale Semiconductor...
Page 546 The final data phase occurs in cycle 6. Another agent cannot start an access until cycle 8. A provision in the specification allows the current master to start another transfer in cycle 7 when certain conditions apply. Refer to fast back-to-back transfers in the PCI specification for more details. Freescale Semiconductor 22-29...
Page 547 PCI_TRDY negates, it is considered a target disconnect without a transfer. See the PCI specification for more details. PCI_CLK PCI_FRAME PCI_AD Byte Enables Byte Enables PCI_CBE PCI_IRDY PCI_TRDY (Wait) PCI_DEVSEL PCI_STOP Address Data Data Phase Phase 1 Phase 2 Figure 22-36. PCI Write Terminated by Target 22-30 Freescale Semiconductor...
Page 548: Pci Bus Commands
Cache line wrap implements if internal bus is the transaction initiator and also wraps. 1101 command transfers a 64-bit DUAL ADDRESS DUAL ADDRESS CYCLE address (in two 32-bit address cycles) to 64-bit addressable CYCLE devices. This device does not respond to this command. Freescale Semiconductor 22-31...
Page 549 Reads from the PCI controller, implemented as delayed reads, always disconnect at the cache line boundary. The PCI controller is not optimized for wrapping bursts. 22-32 Freescale Semiconductor...
Page 550 PCI bus the bridge that owns the PCI bus has already performed the bus number comparison and verified the request targets a device on its bus. Figure 22-37 shows the contents of the AD bus during the address phase of the Type 0 configuration access. Freescale Semiconductor 22-33...
Page 551 If the bus number matches, it should claim and pass the configuration access onto its secondary bus as a Type 0 configuration access, decoding the device 22-34 Freescale Semiconductor...
Page 552: Configuration Interface
If the PCI controller is the host device or configuring master, the internal bus interface configures the PCI Controller. An external master would configure the PCI controller through the external PCI bus. More information on the standard PCI configuration register is in the PCI Local Bus Specification, Revision 2.2. Freescale Semiconductor 22-35...
Page 553: Internal Bus Initiator Interface
If the target for an internal bus read from PCI disconnects part way through the burst, the PCI controller may have to manage a local memory access from an alternate 22-36 Freescale Semiconductor...
Page 554: Endian Translation
Data Bus Byte Lanes HADDR HSIZE [1:0] [2:0] [1:0] [3:0] 31:24 23:16 15:8 31:24 23:16 15:8 — — — 1110 — — — — — — 1101 — — — — — — 1011 — — — Freescale Semiconductor 22-37...
Page 555: Configuration Mechanism
Type 0 translation function performed on the contents of the configuration address register to the PCI_AD[31:0] signals on the PCI bus during the address phase of the configuration cycle (this only applies when the PCICAR[E] bit is set). 22-38 Freescale Semiconductor...
Page 556 AD11 0_1100 AD12 0_1101 AD13 0_1110 AD14 0_1111 AD15 1_0000 AD16 1_0001 AD17 1_0010 AD18 1_0011 AD19 1_0100 AD20 1_0101 AD21 1_0110 AD22 1_0111 AD23 1_1000 AD24 1_1001 AD25 1_1010 AD26 1_1011 AD27 1_1100 AD28 1_1101 AD29 Freescale Semiconductor 22-39...
Page 557 PCI bus should respond to the and return INTERRUPT ACKNOWLEDGE the interrupt vector on the data bus during the data phase. The size of the interrupt vector returned is indicated by the value driven on the PCI_CBE[3:0] signals. 22-40 Freescale Semiconductor...
Page 558: Special Cycle Transactions
(PCI_AD[31:16]). The PCI SIG steering committee assign the message encodings. Table 22-30 provides the current list of defined encodings. SPECIAL CYCLE Table 22-30. Special Cycle Message Encodings PCI_AD[15:0] Message 0x0000 SHUTDOWN 0x0001 HALT 0x0002 x86 architecture-specific 0x0003 – 0xFFFF — Freescale Semiconductor 22-41...
Page 559: Internal Bus Target Interface
All other target memory transactions translate into internal bus master transactions. There are address translation registers for each unique PCIBARn register initialized before data transfer can begin. These address registers correspond to BAR0–5 in PCI Type 00h configuration space register 22-42 Freescale Semiconductor...
Page 560: Reads From Local Memory
PCI master. Otherwise, the PCI controller does not store the prefetched data. If the next Freescale Semiconductor 22-43...
Page 561 The internal bus does not support misaligned operations; therefore, it is recommended that software attempts to transfer contiguous code and data where possible. Non-contiguous transfers degrade performance. Table 22-32 Table 22-33 show PCI-to-internal bus transaction data translation. 22-44 Freescale Semiconductor...
Page 562 Table 22-33. Non-Contiguous PCI to Internal Bus Transfers (All Require Two Internal Bus Accesses) PCI Bus Internal Bus Data Bus Byte Lanes Data Bus Byte Lanes HADDR BE[3:0] AD[1:0] [1:0] 31:24 23:16 15:8 31:24 23:16 15:8 1010 0110 0101 0010 0100 Freescale Semiconductor 22-45...
Page 563: Pci Arbiter
If all masters are programmed to the same group and only one master is assigned to the low-priority group, no priority distinction among masters exists. 22-46 Freescale Semiconductor...
Page 564 If, after this sequence completes, all devices request the bus (including now device 1), the arbiter assigns PCI_GNT to device 1 because it is the longest since device 1 used the bus (it has highest priority). After all requests are serviced, the priority resets to the initial state. Freescale Semiconductor 22-47...
Page 565: Arbitration Latency
Three master devices illustrate how an arbiter may alternate bus accesses. (Assume device 0, device 1, and device 2 are assigned the same priority group and no other masters request use of the bus.) 22-48 Freescale Semiconductor...
Page 566 2 while device 0 and device 1 request use of the PCI bus (Assume device 0, device 1, and device 2 are assigned the same priority group and no other masters request use of the bus). Freescale Semiconductor 22-49...
Page 567: Bus Parking
The parking mode bit in the PCI arbiter control register, PACR[PKMD], determines the parking operation of the arbiter as shown in Table 22-34. In general, parking with the last master that acquired the bus can gain better system performance. 22-50 Freescale Semiconductor...
Page 568 A status bit is set when any master times out. If the corresponding interrupt enable bit is set, a CPU interrupt asserts. Software can query the status bits to detect a broken master in the PCI system. (See Section 22.3.3.2, “PCI Arbiter Status Register (PASR).”) Freescale Semiconductor 22-51...
Page 569: Pci Clock Scheme
66 MHz operation is subject to system clocking restraints. The PCI bus clock to external PCI devices generates from an external PLL, while the internal PCI clock generates from the Coldfire processor’s internal PLL. The internal bus clock is always faster than the PCI clock. 22-52 Freescale Semiconductor...
Page 570: Application Information
The use of the PCI configuration address register along with the initiator window registers provides many possibilities for PCI command and address generation. Table 22-16 shows how the PCI controller accepts read and write requests from an internal bus master and decodes them to different address ranges resulting Freescale Semiconductor 22-53...
Page 571: Address Translation
Values programmed to the PCIBARn registers of the PCI Type 00h configuration space determine location. These inbound memory window sizes are fixed in size. The PCISCR[M] bit must be set before any inbound memory window can be accessed. Otherwise, the PCI controller does not respond to PCI memory transactions. 22-54 Freescale Semiconductor...
Page 572 System Memory Translation Base Address 0 Recommended Initiator PCI Space Windows PCI Controller PCI Controller Memory BAR5 PCITBATR5 Inbound Address SDRAM Space Translation Translation PCI Controller PCI Controller Memory Base Address5 BAR0 Figure 22-44. Inbound Address Map Freescale Semiconductor 22-55...
Page 573: Outbound Address Translation
Non-Prefetchable Memory Window 1 Translation Address = 0x70 Figure 22-45. Outbound Address Map 22.5.2.3 Base Address Register Overview Table 22-37 shows the available accessibility for all PCI associated base address and translation address registers in the PCI controller. 22-56 Freescale Semiconductor...
Page 574 Table 22-38. Status Register Summary Internal Bus Internal Bus Status Interrupt Register Function Target Initiator Register Generated Interface Interface PCISCR PCI Status/Command Register None PCIGSCR PCI Global Status/Control Register PCI controller interrupt PCIISR PCI Initiator Status Register PCI controller interrupt Freescale Semiconductor 22-57...
Page 575 PCI Bus Controller 22-58 Freescale Semiconductor...
Page 576: Introduction
Ultra DMA modes 0, 1, 2, 3 and 4 with bus clock of 50 MHz or higher • Ultra DMA mode 5 with bus clock of 80 Mhz or higher The ATA interface has 2 busses connected: Freescale Semiconductor 23-1...
Page 577: Features
ATA bus during write. PIO accesses can happen to the bus at any time, even during a running ATA DMA transfer. In this case, the DMA transfer pauses, the PIO cycle completes, and the DMA transfer resumes. 23-2 Freescale Semiconductor...
Page 578: External Signal Description
ATA bus DMA acknowledge ATA_INTRQ ATA bus interrupt request — ATA_IORDY ATA bus I/O channel ready — ATA_DATA[15:0] ATA data bus (little-endian) Hi-Z Tri-state I/O This signal is a standard ATA bus signal. It conforms with the ATA specification. Freescale Semiconductor 23-3...
Page 579: Detailed Signal Descriptions
This input signal is the ATA bus interrupt request. The device asserts it when it wants to interrupt the host CPU. 23.2.1.9 ATA I/O Ready (ATA_IORDY) This input signal is the ATA bus I/O channel ready signal. It has three functions: 23-4 Freescale Semiconductor...
Page 580: Memory Map/Register Definition
23.3.2/23-7 0x9000_0011 TIME_MLIX—t UDMA timing register 0x01 23.3.2/23-7 0x9000_0012 TIME_DVH—t UDMA timing register 0x01 23.3.2/23-7 0x9000_0013 TIME_DZFS—t UDMA timing register 0x01 23.3.2/23-7 dzfs 0x9000_0014 TIME_DVS—t UDMA timing register 0x01 23.3.2/23-7 0x9000_0015 TIME_CVH—t UDMA timing register 0x01 23.3.2/23-7 Freescale Semiconductor 23-5...
Page 581: Endianness
The ATA interface works in big endian mode.The few 16-bit and 32-bit registers represent strings of 2 or 4 bytes. The byte order in the 16-bit or 32-bit register is as follows: • Big endian, 32-bit register — bits [31:24]: byte 0 — bits [23:16]: byte 1 23-6 Freescale Semiconductor...
Page 582: Timing Registers (Time_X)
The FIFO data register reads or writes data to the internal FIFO. It can be accessed as a 16-bit register or as a 32-bit register. Any longword write to the register puts the four bytes written into the FIFO, and any Freescale Semiconductor 23-7...
Page 583: Fifo_Fill Register
FIFO_FILL is a read-only register. Any read to it returns the current number of halfwords present in the FIFO. 23.3.5 ATA Control Register (ATA_CR) Figure 23-6 for illustration of valid bits in the ATA control register and Table 23-4 for description of the bit fields. 23-8 Freescale Semiconductor...
Page 584: Interrupt Registers
Interrupt request. Bits 3–6 of the interrupt registers control ATA interrupts. A request to the interrupt controller generates if one of the four bits is set in the interrupt status register (ATA_ISR), while the same bit is set in the interrupt enable register (ATA_IER). Freescale Semiconductor 23-9...
Page 585 ATA_ISR and ATA_IER registers, an interrupt is requested to the CPU. The ATA_ICR register has no influence on this bit. 0 Activity on the ATA bus 1 No activity on the ATA bus, engine is idle 23-10 Freescale Semiconductor...
Page 586 0 FIFO overflow interrupt disabled 1 FIFO overflow interrupt enabled ATA controller idle interrupt enable. IDLE 0 Idle interrupt disabled 1 Idle interrupt enabled ATA interrupt request enable. 0 Interrupt request disabled 1 Interrupt request enabled 2–0 Reserved. Freescale Semiconductor 23-11...
Page 587: Fifo Alarm Register (Fifo_Alarm)
If a read or write access is made to one of these registers, read or write maps to a PIO read or write cycle on the ATA bus, and the corresponding register in the device attached to the ATA bus 23-12 Freescale Semiconductor...
Page 588: Functional Description
= time_2r * T - (tskew1 + tskew2 + tskew5) TIME_2R t9(min) = time_9 * T - (tskew1 + tskew2 + tskew6) TIME_9 t5(min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 if not met, increase TIME_2 Freescale Semiconductor 23-13...
Page 589 = time_2w * T - (tskew1 + tskew2 + tskew5) TIME_2W t9(min) = time_9 * T - (tskew1 + tskew2 + tskew6) TIME_9 t3(min) = (time_2w - time_on)* T - (tskew1 + tskew2 +tskew5) If not met, increase TIME_2W 23-14 Freescale Semiconductor...
Page 590 Figure 23-12. 23.4.1.2 Multiword DMA Mode Timing Diagrams In multiword DMA mode, see Figure 23-13 for read timing diagram and Figure 23-14 for write timing diagram. ATA_DMARQ ATA_DA[2:0] ATA_DMACK ATA_DIOR Read Data[15:0] Figure 23-13. MDMA Read Timing Freescale Semiconductor 23-15...
Page 591 Figure 23-14. tk1 in the UDMA figures equals (tk -2*T) 23.4.1.3 Ultra DMA In Timing Diagrams UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA are provided. 23-16 Freescale Semiconductor...
Page 592 Figure 23-15. UDMA in Transfer Start Timing Diagram Figure 23-16 shows timing for host terminating UDMA in transfer. ATA_DA[2:0] ATA_DMARQ ATA_DMACK ATA_DIOR ATA_DIOW ATA_IORDY Read Data dzfs Write Data ATA_BUFFER_EN Figure 23-16. UDMA in Host Terminates Transfer Freescale Semiconductor 23-17...
Page 593 There is a special timing requirement in the ATA host requiring the internal DIOW to only go high three clocks after the last active edge on the DSTROBE signal. The equation on this line tries to capture this constraint. 2. Make ton and toff big enough to avoid bus contention. 23-18 Freescale Semiconductor...
Page 594 Figure 23-18. UDMA Out Transfer Start Timing Diagram Figure 23-19 shows timing for host terminating UDMA out transfer. ATA_DA[2:0] ATA_DMARQ ATA_DMACK ATA_DIOW ATA_DIOR Write Data ATA_IORDY ATA_BUFFER_EN Figure 23-19. UDMA Out Host Terminates Transfer Figure 23-20 shows timing for device terminating UDMA out transfer. Freescale Semiconductor 23-19...
Page 595 > 0 tli2 tli2 > 0 tli3 tli3 > 0 tcvh tcvh tcvh = (time_cvh *T) - (tskew1 + tskew2) TIME_CVH ton = time_on * T - tskew1 toff toff = time_off * T - tskew1 23-20 Freescale Semiconductor...
Page 596: Resetting Ata Bus
(DMA in transfer). In DMA receive mode, the protocol engine transfers data from the drive to the FIFO using multiword DMA or ultra DMA protocol. The transfer pauses when: • The FIFO is full. Freescale Semiconductor 23-21...
Page 597 9. On end-of-transfer, the host or host DMA should wait until ATA_ISR[IDLE] is set; next read, the remaining halfwords from the FIFO and transfer these to memory. NOTE There may be less than <packetsize> remaining bytes, so the transfer is not automatic by the DMA. 23-22 Freescale Semiconductor...
Page 598: Using Dma Mode To Transmit Data To Ata Bus
Consult the ATA specification for more information on how to communicate with the drive. 7. When the drive now requests DMA transfer by asserting ATA_DMARQ, the ATA interface acknowledges with ATA_DMACK, and the transfer starts. Data is transferred automatically from the FIFO, and also from host memory to FIFO. Freescale Semiconductor 23-23...
Page 599 These reads cause the running DMA to pause; after the read completes, the DMA resumes. The host can also wait until the drive asserts ATA_INTRQ. This also indicates end of transfer. On end-of-transfer, no extra FIFO manipulations are needed. 23-24 Freescale Semiconductor...
Page 600 Advanced Technology Attachment (ATA) Freescale Semiconductor 23-25...
Page 601 Freescale Semiconductor...
Page 602: Introduction
CAU. CA0-CA3 DES / AES Row Result Register File Hash Operand1 Command Datapath Decode Control Figure 24-1. Top Level CAU Block Diagram 24.1.2 Overview The CAU supports acceleration of the following algorithms: • • 3DES • • Freescale Semiconductor 24-2...
Page 603: Features
General purpose register 1 (CA1) 0x0000_0000 24.2.3/24-5 General purpose register 2 (CA2) 0x0000_0000 24.2.3/24-5 General purpose register 3 (CA3) 0x0000_0000 24.2.3/24-5 General purpose register 4 (CA4) — — — 0x0000_0000 24.2.3/24-5 General purpose register 5 (CA5) — — — 0x0000_0000 24.2.3/24-5 24-3 Freescale Semiconductor...
Page 604: Cau Status Register (Casr)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-3. CAU Accumulator Register (CAA) Table 24-3. CAA Field Descriptions Field Description 31–0 Accumulator. Stores results of various CAU commands. Freescale Semiconductor 24-4...
Page 605: Programming Model
Table 24-5 shows how the CAU supports a single command ( ) for store instructions and 21 commands for the load instructions. The CAU only supports longword operations. A CAU command can be issued every clock cycle. 24-5 Freescale Semiconductor...
Page 606: Cau Commands
CAA <<< 5 CAA,   CA0, CA0 CA1,  CA1 <<< 30 CA2,   CA3, CA3   cp0ld Message Digest Shift 0x140 CAA, CAA CA1,   CA2, CA2 CA3,  cp0ld Illegal Command 0x1F0 CASR[0] Freescale Semiconductor 24-6...
Page 607 Command Example RADR Operand CAx Before CAx After 0x0102_0304 0xA0B0_C0D0 0xA4B3_C2D1 24.3.3.6 Add Register to Accumulator ( ADRA cp0ld.l #ADRA+CAx command adds CAx to CAA and stores the result in CAA. ADRA 24.3.3.7 Exclusive Or ( cp0ld.l <ea>,#XOR+CAx 24-7 Freescale Semiconductor...
Page 608 <ea>,#AESIC+CAx command performs an exclusive-or operation of the source operand specified by <ea> on the AESIC contents of CAx followed by the AES inverse mix column operation on that result and stores the result back in CAx. Freescale Semiconductor 24-8...
Page 609 CA0 and CA1. Table 24-9 defines the specific shift function performed based on the KSx field. Table 24-9. Key Shift Function Codes Shift Function Code Define KSL1 Left 1 KSL2 Left 2 24-9 Freescale Semiconductor...
Page 610 SHA-1. The following source and destination assignments are made: CAA=CAA<<<5, CA0=CAA, CA1=CA0, CA2=CA1<<<30, CA3=CA2, CA4=CA3. 1.The DES algorithm numbers the most significant bit of a block as bit 1 and the least significant as bit 64. Freescale Semiconductor 24-10...
Page 611: Application/Initialization Information
.set CASR,0x0 .set CAA,0x1 .set CA0,0x2 .set CA1,0x3 .set CA2,0x4 .set CA3,0x5 .set CA4,0x6 .set CA5,0x7 ; CAU Commands .set CNOP,0x000 .set LDR,0x010 .set STR,0x020 .set ADR,0x030 .set RADR,0x040 .set ADRA,0x050 .set XOR,0x060 .set ROTL,0x070 .set MVRA,0x080 24-11 Freescale Semiconductor...
Page 612 ; MD5 G() CA1&CA3 | CA2&~CA3 .set HFH,0x2 ; MD5 H(), SHA Parity() CA1^CA2^CA3 .set HFI,0x3 ; MD5 I() CA2^(CA1|~CA3) .set HFC,0x4 ; SHA Ch() CA1&CA2 ^ ~CA1&CA3 .set HFM,0x5 ; SHA Maj() CA1&CA2 ^ CA1&CA3 ^ CA2&CA3 Freescale Semiconductor 24-12...
Page 613: Introduction
– Current time using highest precision possible – Mouse and keyboard motions (or equivalent if being used on a cell phone or PDA) – Other entropy supplied directly by the user Freescale Semiconductor 25-1...
Page 614: Memory Map/Register Definition
0 RNGA is not in sleep mode. 1 RNGA is in sleep mode. Clear interrupt. Writing a 1 to this bit clears the error interrupt and RNGSR[EI]. This bit is self-clearing, 0 Do not clear error interrupt. 1 Clear error interrupt. Freescale Semiconductor 25-2...
Page 615: Rng Status Register (Rngsr)
0 FIFO not read while empty. 1 FIFO read while empty. FIFO underflow. Signals FIFO underflow. Reset by reading RNGSR. 0 FIFO not read while empty since last read of RNGSR. 1 FIFO read while empty since last read of RNGSR. 25-3 Freescale Semiconductor...
Page 616: Rng Entropy Register (Rnger)
Random Output Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25-4. RNGOUT Freescale Semiconductor 25-4...
Page 617: Functional Description
RNG Core Engine The core engine block contains the logic that generates random data. The logic within the core engine contains the internal shift registers, as well as the logic that generates the two oscillator based clocks. This 25-5 Freescale Semiconductor...
Page 618: Initialization/Application Information
3. Write to the RNG control register and set the interrupt mask, high assurance, and GO bits. 4. Poll RNGSR[OFL] to check for random data in the FIFO. 5. Read available random data from RNGOUT. 6. Repeat steps 3 and 4 as needed. Freescale Semiconductor 25-6...
Page 619: Introduction
Ethernet transceiver. The FECs support the 10/100 Mbps MII, 10/100 Mbps reduced MII, and the 10 Mbps-only 7-wire interface. NOTE The pin multiplexing and control module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 16, “Pin Multiplexing and Control”) prior to configuring the FECs. Freescale Semiconductor 26-1...
Page 620: Block Diagram
Initialization (those internal registers not initialized by you or hardware) • High level control of the DMA channels (initiating DMA transfers) • Interpreting buffer descriptors • Address recognition for receive frames • Random number generation for transmit collision backoff timer Freescale Semiconductor 26-2...
Page 621: Features
Programmable max frame length supports IEEE 802.1 VLAN tags and priority • Support for full-duplex operation (200 Mbps throughput) with a minimum internal bus clock rate of 50 MHz • Support for half-duplex operation (100 Mbps throughput) with a minimum internal bus clock rate of 50 MHz 26-3 Freescale Semiconductor...
Page 622: Full And Half Duplex Operation
The reduced media independent interface (RMII) is a low cost alternative to the IEEE 802.3 MII standard. This interface provides the functionality of the MII interface on a total of 8 pins instead of 18. The RMII interface for 10/100 Ethernet MAC-PHY interface was defined by an industry consortium and is not Freescale Semiconductor 26-4...
Page 623: Address Recognition Options
Assertion of FEC_RXDV must start no later than the SFD and exclude any EOF. In RMII mode, this pin also generates the CRS signal. FEC_RXD0 This pin contains the Ethernet input data transferred from PHY to the media-access controller when FEC_RXDV is asserted. 26-5 Freescale Semiconductor...
Page 624: Memory Map/Register Definition
Table 26-2. Module Memory Map Address Function 0xFC03_0000 – FC03_01FF FEC0 Control/Status Registers 0xFC03_0200 – FC03_02FF FEC0 MIB Block Counters 0xFC03_4000 – FC03_41FF FEC1 Control/Status Registers 0xFC03_4200 – FC03_42FF FEC1 MIB Block Counters Freescale Semiconductor 26-6...
Page 625 Descriptor Individual Lower Address Register (IALRn) Undefined 26.4.16/26-24 0xFC03_411C 0xFC03_0120 Descriptor Group Upper Address Register (GAURn) Undefined 26.4.17/26-24 0xFC03_4120 0xFC03_0124 Descriptor Group Lower Address Register (GALRn) Undefined 26.4.18/26-25 0xFC03_4124 0xFC03_0144 Transmit FIFO Watermark (TFWRn) 0x0000_0000 26.4.19/26-25 0xFC03_4144 26-7 Freescale Semiconductor...
Page 626: Mib Block Counters Memory Map
MIB counters. Counters for transmit and receive full duplex flow control frames are also included. Table 26-4. MIB Counters Memory Map Address Register FEC0 FEC1 0xFC03_0200 Count of frames not counted correctly (RMON_T_DROPn) 0xFC03_4200 0xFC03_0204 RMON Tx packet count (RMON_T_PACKETSn) 0xFC03_4204 0xFC03_0208 RMON Tx broadcast packets (RMON_T_BC_PKTn) 0xFC03_4208 Freescale Semiconductor 26-8...
Page 627 RMON Tx Octets (RMON_T_OCTETSn) 0xFC03_4244 0xFC03_0248 Count of transmitted frames not counted correctly (IEEE_T_DROPn) 0xFC03_4248 0xFC03_024C Frames transmitted OK (IEEE_T_FRAME_OKn) 0xFC03_424C 0xFC03_0250 Frames transmitted with single collision (IEEE_T_1COLn) 0xFC03_4250 0xFC03_0254 Frames transmitted with multiple collisions (IEEE_T_MCOLn) 0xFC03_4254 26-9 Freescale Semiconductor...
Page 628 RMON Rx packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZEn) 0xFC03_4298 0xFC03_029C RMON Rx packets < 64 bytes, bad CRC (RMON_R_FRAGn) 0xFC03_429C 0xFC03_02A0 RMON Rx packets > MAX_FL bytes, bad CRC (RMON_R_JABn) 0xFC03_42A0 0xFC03_02A4 Reserved (RMON_R_RESVD_0n) 0xFC03_42A4 0xFC03_02A8 RMON Rx 64 byte packets (RMON_R_P64n) 0xFC03_42A8 Freescale Semiconductor 26-10...
Page 629: Ethernet Interrupt Event Registers (Eir0 & Eir1)
Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB, and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR, BABR, BABT, LC, and RL. Interrupts resulting from internal errors are HBERR and UN. 26-11 Freescale Semiconductor...
Page 630 Transmit frame interrupt. Indicates a frame has been transmitted and the last corresponding buffer descriptor has been updated. Transmit buffer interrupt. Indicates a transmit buffer descriptor has been updated. Receive frame interrupt. Indicates a frame has been received and the last corresponding buffer descriptor has been updated. Freescale Semiconductor 26-12...
Page 631: Interrupt Mask Registers (Eimr0 & Eimr1)
1 is written to the EIRn bit (write 1 to clear) or a 0 is written to the EIMRn bit. Address: 0xFC03_0008 (EIMR0) Access: User read/write 0xFC03_4008 (EIMR1) BABR BABT GRA Reset Reset Figure 26-3. Ethernet Interrupt Mask Register (EIMRn) 26-13 Freescale Semiconductor...
Page 632: Receive Descriptor Active Registers (Rdar0 & Rdar1)
When the register is written, the TDAR bit is set. This value is independent of the data actually written by the user. When set, the FEC polls the transmit descriptor ring and processes transmit frames (provided ECRn[ETHER_EN] is also set). After the FEC polls a transmit descriptor that is a ready bit not set, FEC Freescale Semiconductor 26-14...
Page 633: Ethernet Control Registers (Ecr0 & Ecr1)
Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26-6. Ethernet Control Register (ECRn) Table 26-9. ECRn Field Descriptions Field Description 31–2 Reserved, must be cleared. 26-15 Freescale Semiconductor...
Page 634: Mii Management Frame Registers (Mmfr0 & Mmfr1)
11 Read frame operation, but not MII compliant. 27–23 PHY address. This field specifies one of up to 32 attached PHY devices. 22–18 Register address. This field specifies one of up to 32 registers within the specified PHY device. Freescale Semiconductor 26-16...
Page 635: Mii Speed Control Registers (Mscr0 & Mscr1)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26-8. MII Speed Control Register (MSCRn) 26-17 Freescale Semiconductor...
Page 636: Mib Control Registers (Mibc0 & Mibc1)
MIB block operation. For example, to clear all MIB counters in RAM: 1. Disable the MIB block 2. Clear all the MIB RAM locations 3. Enable the MIB block Freescale Semiconductor 26-18...
Page 637: Receive Control Registers (Rcr0 & Rcr1)
MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame receive buffer descriptor. The recommended default value to be programmed is 1518 or 1522 if VLAN tags are supported. 26-19 Freescale Semiconductor...
Page 638 1 FEC configured for RMII operation, only if the MII_MODE bit is set. To summarize the various settings see the below table. PAR_FEC[2:0] RMII_MODE MII_MODE Description PAR_FEC[6:5] (Equation 26-2) GPIO mode Non-FEC functions 7-wire mode RMII mode Reserved Reserved 7-wire mode MII mode 7–6 Reserved, must be cleared. Freescale Semiconductor 26-20...
Page 639: Transmit Control Registers (Tcr0 & Tcr1)
Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data frames. If the transmitter pauses due to user assertion of GTS or reception of a PAUSE frame, the MAC may continue transmitting a MAC Control PAUSE frame. 26-21 Freescale Semiconductor...
Page 640: Physical Address Lower Registers (Palr0 & Palr1)
4 and 5 of the 6-byte Source Address field when transmitting PAUSE frames. Bits 15:0 of PAURn contain a constant type field (0x8808) for transmission of PAUSE frames. The upper 16 bits of this register are not reset and you must initialize it. Freescale Semiconductor 26-22...
Page 641: Opcode/Pause Duration Registers (Opd0 & Opd1)
IAURn contains the upper 32 bits of the 64-bit individual address hash table. The address recognition process uses this table to check for a possible match with the destination address (DA) field of receive frames with an individual DA. This register is not reset and you must initialize it. 26-23 Freescale Semiconductor...
Page 642: Descriptor Individual Lower Address Registers (Ialr0 & Ialr1)
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 26-17. Descriptor Group Upper Address Register (GAURn) Freescale Semiconductor 26-24...
Page 643: Descriptor Group Lower Address Registers (Galr0 & Galr1)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26-19. Transmit FIFO Watermark Register (TFWRn) 26-25 Freescale Semiconductor...
Page 644: Fifo Receive Bound Registers (Frbr0 & Frbr1)
FRSRn. The receive FIFO uses addresses from FRSRn to FRBRn inclusive. Hardware initializes the FRSRn register at reset. FRSRn only needs to be written to change the default value. Freescale Semiconductor 26-26...
Page 645: Receive Descriptor Ring Start Registers (Erdsr0 & Erdsr1)
26.4.23 Transmit Buffer Descriptor Ring Start Registers (ETSDR0 & ETSDR1) ETSDRn provides a pointer to the start of the circular transmit buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly 26-27 Freescale Semiconductor...
Page 646: Receive Buffer Size Registers (Emrbr0 & Emrbr1)
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 26-24. Receive Buffer Size Register (EMRBRn) Freescale Semiconductor 26-28...
Page 647: Buffer Descriptors
DMA engine BD pointers are reset to point to the starting transmit and receive BDs. The buffer descriptors are not initialized by hardware during reset. At least one transmit and receive buffer descriptor must be initialized by software before ECRn[ETHER_EN] is set. 26-29 Freescale Semiconductor...
Page 648 L set and information written to the status bits (M, BC, MC, LG, NO, CR, OV, TR). Some of the status bits are error indicators which, if set, indicate the receive frame should be discarded and not given to higher layers. The frame status/length information is written into the receive FIFO following the end of the frame Freescale Semiconductor 26-30...
Page 649 Offset + 0 Last in frame. Written by the FEC. 0 The buffer is not the last in a frame. 1 The buffer is the last in a frame. 26-31 Freescale Semiconductor...
Page 650 Ethernet Transmit Buffer Descriptors (TxBD0 & TxBD1) Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs. The Ethernet controller confirms transmission by clearing the ready bit (TxBDn[R]) when DMA of the Freescale Semiconductor 26-32...
Page 651 Reserved, must be cleared. Offset + 2 15–0 Data length, written by user. Data Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never Length modified by the FEC. 26-33 Freescale Semiconductor...
Page 652: Initialization Sequence
Descriptor Controller block Halt operation 26.5.3 User Initialization (Prior to Setting ECRn[ETHER_EN]) You need to initialize portions the FEC prior to setting the ECRn[ETHER_EN] bit. The exact values depend on the particular application. The sequence is not important. Freescale Semiconductor 26-34...
Page 653: Microcontroller Initialization
After the microcontroller initialization sequence is complete, hardware is ready for operation. Table 26-34 shows microcontroller initialization operations. Table 26-34. Microcontroller Initialization Description Initialize BackOff Random Number Seed Activate Receiver Activate Transmitter Clear Transmit FIFO Clear Receive FIFO 26-35 Freescale Semiconductor...
Page 654: Network Interface Options
Receive Data FECn_RXD[3:0] Receive Error FECn_RXER Management Data Clock FECn_MDC Management Data FECn_MDIO Input/Output In RMII mode (RCR [MII_MODE] set and RCR [RMII_MODE] cleared), the EMAC supports 8 external signals. These signals are shown in Table 26-36 below. Freescale Semiconductor 26-36...
Page 655: Fec Frame Transmission
60 bit times. If so, transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive). See Section 26.5.17.1, “Transmission Errors,” for more details. 26-37 Freescale Semiconductor...
Page 656 The FEC software driver ensures a minimum frame size, n. The minimum number of TxBDs is then (Tx FIFO Size  (n + 4)) rounded up to the nearest integer (though the result cannot be less than three). The default Tx FIFO size is 192 bytes; this size is programmable. Freescale Semiconductor 26-38...
Page 657: Fec Frame Reception
The Ethernet controller then waits for a new frame. 26.5.9 Ethernet Address Recognition The FECs filter the received frames based on destination address (DA) type — individual (unicast), group (multicast), or broadcast (all-ones group address). The difference between an individual address and a 26-39 Freescale Semiconductor...
Page 658 MISS bit in the receive buffer descriptor is set; otherwise, the frame is rejected. In general, when a frame is rejected, it is flushed from the FIFO. Freescale Semiconductor 26-40...
Page 659 Set BC bit in Rcv BD if broadcast BC_REJ - field in RCRn register (BroadCast REJect) PROM - field in RCRn register (PROMiscous mode) Pause Frame - valid PAUSE frame received Figure 26-27. Ethernet Address Recognition—Receive Block Decisions 26-41 Freescale Semiconductor...
Page 660: Hash Algorithm
56/64 (87.5%) of the group address frames from reaching memory. Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. The effectiveness of the hash table declines as the number of addresses increases. Freescale Semiconductor 26-42...
Page 661 35FF_FFFF_FFFF B5FF_FFFF_FFFF 95FF_FFFF_FFFF D5FF_FFFF_FFFF F5FF_FFFF_FFFF DBFF_FFFF_FFFF FBFF_FFFF_FFFF BBFF_FFFF_FFFF 8BFF_FFFF_FFFF 0BFF_FFFF_FFFF 3BFF_FFFF_FFFF 7BFF_FFFF_FFFF 5BFF_FFFF_FFFF 27FF_FFFF_FFFF 0x10 07FF_FFFF_FFFF 0x11 57FF_FFFF_FFFF 0x12 77FF_FFFF_FFFF 0x13 F7FF_FFFF_FFFF 0x14 C7FF_FFFF_FFFF 0x15 97FF_FFFF_FFFF 0x16 A7FF_FFFF_FFFF 0x17 99FF_FFFF_FFFF 0x18 B9FF_FFFF_FFFF 0x19 F9FF_FFFF_FFFF 0x1A C9FF_FFFF_FFFF 0x1B 26-43 Freescale Semiconductor...
Page 662 0x29 1FFF_FFFF_FFFF 0x2A 3FFF_FFFF_FFFF 0x2B BFFF_FFFF_FFFF 0x2C 9FFF_FFFF_FFFF 0x2D DFFF_FFFF_FFFF 0x2E EFFF_FFFF_FFFF 0x2F 93FF_FFFF_FFFF 0x30 B3FF_FFFF_FFFF 0x31 F3FF_FFFF_FFFF 0x32 D3FF_FFFF_FFFF 0x33 53FF_FFFF_FFFF 0x34 73FF_FFFF_FFFF 0x35 23FF_FFFF_FFFF 0x36 13FF_FFFF_FFFF 0x37 3DFF_FFFF_FFFF 0x38 0DFF_FFFF_FFFF 0x39 5DFF_FFFF_FFFF 0x3A 7DFF_FFFF_FFFF 0x3B Freescale Semiconductor 26-44...
Page 663: Full Duplex Flow Control
(TCRn[TFC_PAUSE]). After TCRn[TFC_PAUSE] is set, the transmitter sets TCRn[GTS] internally. When the transmission of data frames stops, the EIRn[GRA] (graceful stop complete) interrupt asserts and the pause frame is transmitted. TCRn[TFC_PAUSE,GTS] are then cleared internally. You must specify the desired pause duration in the OPDn register. 26-45 Freescale Semiconductor...
Page 664: Inter-Packet Gap (Ipg) Time
DMA’d to/from external memory. It may be necessary to pace the frames on the transmit side and/or limit the size of the frames to prevent transmit FIFO underruns and receive FIFO overflows. For external loopback, clear RCRn[LOOP] and RCRn[DRT], and configure the external transceiver for loopback. Freescale Semiconductor 26-46...
Page 665: Rmii Loopback
EIRn[UN] is set. The FEC then continues to the next transmit buffer descriptor and begin transmitting the next frame. The UN interrupt is asserted if enabled in the EIMRn register. 26-47 Freescale Semiconductor...
Page 666 CRC error can be ignored if checking is not required. 26.5.17.2.4 Frame Length Violation When the receive frame length exceeds MAX_FL bytes the BABR interrupt is generated, and RxBDn[LG] is set. The frame is not truncated unless the frame length exceeds 2047 bytes. Freescale Semiconductor 26-48...
Page 667 Fast Ethernet Controllers (FEC0 and FEC1) 26.5.17.2.5 Truncation When the receive frame length exceeds 2047 bytes, frame is truncated and RxBDn[TR] is set. 26-49 Freescale Semiconductor...
Page 668: Introduction
NOTE This device contains SSI bits to control the clock rate and the SSI DMA request sources within the chip configuration module (CCM). See Chapter 11, “Chip Configuration Module (CCM),” for detailed information on these bit fields. Freescale Semiconductor 27-1...
Page 669: Overview
The SSI is a full-duplex serial port that allows the processor to communicate with a variety of serial devices. Such serial devices are: • Standard codecs • Digital signal processors (DSPs) • Microprocessors • Peripherals ® • Audio codecs that implement the inter-IC sound bus (I S) and the Intel AC97 standards 27-2 Freescale Semiconductor...
Page 670: Features
Normal mode • Network mode • Gated clock mode These modes can be programmed via the SSI control registers. Table 27-1 lists these operating modes and some of the typical applications in which they can be used: Freescale Semiconductor 27-3...
Page 671 In slave modes, the SSI’s programmed frame length setting (DC bits) can be lesser than or equal to the frame length setting of the master (external codec). Section 27.4.1, “Detailed Operating Mode Descriptions,” for more details on the above modes. 27-4 Freescale Semiconductor...
Page 672: External Signal Description
SSI_FS during rising edge of SSI_BCLK. 27.2.5 SSI_RXD — Serial Receive Data The SSI_RXD port is an input and brings serial data into the receive data shift register. Freescale Semiconductor 27-5...
Page 673: Ssi_Txd — Serial Transmit Data
The shift direction can be defined as msb first or lsb first, and there are other options on the clock and frame sync. 27-6 Freescale Semiconductor...
Page 674: Memory Map/Register Definition
0xFC0B_C004 SSI Transmit Data Register 1 (SSI_TX1) 0x0000_0000 27.3.1/27-8 0xFC0B_C008 SSI Receive Data Register 0 (SSI_RX0) 0x0000_0000 27.3.4/27-10 0xFC0B_C00C SSI Receive Data Register 1 (SSI_RX1) 0x0000_0000 27.3.4/27-10 0xFC0B_C010 SSI Control Register (SSI_CR) 0x0000_0000 27.3.7/27-13 0xFC0B_C014 SSI Interrupt Status Register (SSI_ISR) 0x0000_3003 27.3.8/27-15 Freescale Semiconductor 27-7...
Page 675: Ssi Transmit Data Registers 0 And 1 (Ssi_Tx0/1)
Example: If Tx FIFO0 is not in use and you write Data1, Data2 to SSI_TX0, Data2 does not overwrite Data1 and is discarded. Note: Enable SSI (SSI_CR[SSI_EN] = 1) before writing to the SSI transmit data registers 27-8 Freescale Semiconductor...
Page 676: Ssi Transmit Fifo 0 And 1 Registers
They illustrate some possible values for WL, which can be extended for the other values. SSI_TX 12 bits 16 bits 20 bits 24 bits TXSR 16 bits 12 bits SSI_TXD Figure 27-5. Transmit Data Path (TXBIT0=0, TSHFD=0) (msb Alignment) Freescale Semiconductor 27-9...
Page 677: Ssi Receive Data Registers 0 And 1 (Ssi_Rx0/1)
Figure 27-8. Transmit Data Path (TXBIT0=1, TSHFD=1) (lsb Alignment) 27.3.4 SSI Receive Data Registers 0 and 1 (SSI_RX0/1) The SSI_RX0/1 registers store the data received by the SSI. For details on data alignment see Section 27.3.6, “SSI Receive Shift Register (RXSR).” 27-10 Freescale Semiconductor...
Page 678: Ssi Receive Fifo 0 And 1 Registers
SSI_RX is full) after a word has been shifted in. For receiving less than 24 bits of data, the lsb bits are appended with 0. The following figures show the receiver loading and shifting operation. They illustrate some possible values for WL, which can be extended for the other values. Freescale Semiconductor 27-11...
Page 679 RXSR 16 bits 12 bits SSI_RXD Figure 27-11. Receive Data Path (RXBIT0=0, RSHFD=1) (msb Alignment) SSI_RX 12 bits 16 bits 20 bits 24 bits 24 bits SSI_RXD RXSR Figure 27-12. Receive Data Path (RXBIT0=1, RSHFD=0) (lsb Alignment) 27-12 Freescale Semiconductor...
Page 680: Ssi Control Register (Ssi_Cr)
Two channel operation can be enabled for an even number of slots larger than two to optimize usage of both FIFOs. However, TCH should be cleared for an odd number of time slots. 0 Two channel mode disabled 1 Two channel mode enabled Freescale Semiconductor 27-13...
Page 681 Tx and Rx FIFOs are cleared. When SSI is disabled, all internal clocks are disabled (except the register access clock). 0 SSI module is disabled 1 SSI module is enabled 27-14 Freescale Semiconductor...
Page 682: Ssi Interrupt Status Register (Ssi_Isr)
It causes the receive tag interrupt if the SSI_IER[RXT] bit is set. This bit is cleared upon reading the SSI_ATAG register. 0 No change in SSI_ATAG register 1 SSI_ATAG register updated with different value Freescale Semiconductor 27-15...
Page 683 • At least one empty slot in Tx • Tx FIFO1 is full FIFO1 • SSI reset • POR reset Disabled • SSI_TX1 data transferred to • SSI_TX1 is written TXSR • SSI reset • POR reset 27-16 Freescale Semiconductor...
Page 684 Tx FIFO1 all of the following occur any of the following occur Enabled • TXSR is empty • Reading SSI_ISR when TUE1 is • SSI_ISR[TDE1] set Disabled • Transmit time slot occurs • SSI reset • POR reset Freescale Semiconductor 27-17...
Page 685 RFS is set when any of the following occur Normal • RFS is always set • SSI reset • POR reset Network • First time slot received • Starts receiving next time slot • SSI reset • POR reset 27-18 Freescale Semiconductor...
Page 686 Receive FIFO full 0. Similar to description of RFF1, but pertains to Rx FIFO 0 and is not necessary to be in RFF0 two-channel mode for this bit to be set. 0 Space available in receive FIFO 0 1 Receive FIFO 0 is full Freescale Semiconductor 27-19...
Page 687: Ssi Interrupt Enable Register (Ssi_Ier)
The SSI_IER register sets up the SSI interrupts and DMA requests. Address: 0xFC0B_C018 (SSI_IER) Access: User read/write RDMAE RIE TDMAE CMDU Reset RDR1 RDR0 TDE1 TDE0 ROE1 ROE0 TUE1 TUE0 TFS RFF1 RFF0 TFE1 TFE0 Reset Figure 27-16. SSI Interrupt Enable Register (SSI_IER) 27-20 Freescale Semiconductor...
Page 688: Ssi Transmit Configuration Register (Ssi_Tcr)
SSI_TCR bits. However, an SSI reset does not affect the SSI_TCR bits. Address: 0xFC0B_C01C (SSI_TCR) Access: User read/write Reset TFEN1 TFEN0 TFDIR TXDIR TSHFD TSCKP TFSI TFSL TEFS BIT0 Reset Figure 27-17. SSI Transmit Configuration Register (SSI_TCR) Freescale Semiconductor 27-21...
Page 689 (TFSL = 0). The frame sync can also be initiated upon receiving the first bit of data. 0 Transmit frame sync initiated as first bit of data transmits 1 Transmit frame sync is initiated one bit before the data transmits 27-22 Freescale Semiconductor...
Page 690: Ssi Receive Configuration Register (Ssi_Rcr)
RXDIR 0 Gated clock mode disabled 1 Gated clock mode enabled Receive shift direction. Controls whether the msb or lsb is received first in a sample. RSHFD 0 Data received msb first 1 Data received lsb first Freescale Semiconductor 27-23...
Page 691: Ssi Clock Control Register (Ssi_Ccr)
Prescaler range. Controls a fixed divide-by-eight prescaler in series with the variable prescaler. It extends the range of the prescaler for those cases where a slower bit clock is required. 0 Prescaler bypassed 1 Prescaler enabled to divide the clock by 8 27-24 Freescale Semiconductor...
Page 692: Ssi Fifo Control/Status Register (Ssi_Fcsr)
Section 27.4.2.2, “DIV2, PSR and PM Bit Description,” for details regarding settings. 27.3.13 SSI FIFO Control/Status Register (SSI_FCSR) Figure 27-20 for illustration of valid bits in SSI FIFO Control/Status Register and Table 27-13 description of the bit fields in the register. Freescale Semiconductor 27-25...
Page 693 Synchronous Serial Interface (SSI) 0xBASE_2C (SFCSR) Access: User read/write RFCNT1[3:0] TFCNT1[3:0] RFWM1[3:0] TFWM1[3:0] RESET RFCNT0[3:0] TFCNT0[3:0] RFWM0[3:0] TFWM0[3:0] RESET Figure 27-20. SSI FIFO Control/Status Register 27-26 Freescale Semiconductor...
Page 694 10 data word in receive FIFO 1011 11 data word in receive FIFO 1100 12 data word in receive FIFO 1101 13 data word in receive FIFO 1110 14 data word in receive FIFO 1111 15 data word in receive FIFO Freescale Semiconductor 27-27...
Page 695 10 data word in transmit FIFO 1011 11 data word in transmit FIFO 1100 12 data word in transmit FIFO 1101 13 data word in transmit FIFO 1110 14 data word in transmit FIFO 1111 15 data word in transmit FIFO 27-28 Freescale Semiconductor...
Page 696 1110 RFF set when more than or equal to 14 data word have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words 1111 RFF set when 15 data word have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words Freescale Semiconductor 27-29...
Page 697 1110 TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 1 data. 1111 TFE set when there are 15 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO = 0 data. 27-30 Freescale Semiconductor...
Page 698 Transmit FIFO Empty flag, with different settings of the Transmit FIFO WaterMark bits and varying amounts of data in the Tx FIFO. Table 27-18. Status of Transmit FIFO Empty Flag Number of data in Tx-Fifo Transmit FIFO Watermark (TFWM) Freescale Semiconductor 27-31...
Page 699: Ssi Ac97 Control Register (Ssi_Acr)
1 Tag information stored in Rx FIFO 0 Fixed/variable operation. 0 AC97 fixed mode 1 AC97 variable mode AC97 mode enable. Refer to Section 27.4.1.5, “AC97 Mode,” for details of AC97 operation. AC97EN 0 AC97 mode disabled 1 AC97 mode enabled 27-32 Freescale Semiconductor...
Page 700: Ssi Ac97 Command Address Register (Ssi_Acadd)
If the contents of these bits change due to an update, the SSI_ISR[CMDDU] bit is set. During an AC97 read command, 0x0_0000 in time slot #2. Freescale Semiconductor 27-33...
Page 701: Ssi Ac97 Tag Register (Ssi_Atag)
If a change is made to the register contents, the transmission pattern is updated from the next time slot. Transmit mask bits should not be used in I S slave mode. 0 Valid time slot 1 Time slot masked (no data transmitted in this time slot) 27-34 Freescale Semiconductor...
Page 702: Ssi Receive Time Slot Mask Register (Ssi_Rmask)
27.4.1.1.1 Normal Mode Transmit Conditions for data transmission from the SSI in normal mode are: 1. SSI enabled (SSI_CR[SSI_EN] = 1) 2. Enable FIFO and configure transmit and receive watermark if the FIFO is used. Freescale Semiconductor 27-35...
Page 703 The Tx data register is loaded with the data to be transmitted. On arrival of the frame sync, this data is transferred to the transmit shift register 27-36 Freescale Semiconductor...
Page 704 Tx data line is tri-stated at the last inactive edge of the incoming bit clock (during the last bit in a data word). Gated SSI_BCLK Tx Data SSI_TXD SSI_RXD Rx Data Figure 27-28. Normal Mode Timing - Internal Gated Clock Freescale Semiconductor 27-37...
Page 705 In this mode, data is transmitted/received in enabled time slots alternately from/to FIFO 0 and FIFO 1, starting from FIFO 0. The first data word is taken from FIFO 0 and transmitted in the 27-38 Freescale Semiconductor...
Page 706 RE is enabled before the second to last bit of the word. If the RE bit is cleared, the receiver is disabled at the end of the current frame. The SSI module is Freescale Semiconductor 27-39...
Page 707 (0x55). Because the flag is not cleared (Rx data register is not read), the receive overrun error (ROE) flag is set on reception of the next data (0x5E). The ROE flag is cleared by reading the SSI status register followed by reading the Rx data register. 27-40 Freescale Semiconductor...
Page 708 In gated clock mode, presence of the clock indicates that valid data is on the SSI_TXD or SSI_RXD signals. For this reason, no frame sync is needed in this mode. After transmission of data completes, the clock is pulled to the inactive state. Gated clocks are allowed for the transmit and receive Freescale Semiconductor 27-41...
Page 709 Figure 27-31. Internal Gated Mode Timing - Rising Edge Clocking/Falling Edge Latching SSI_BCLK SSI_TXD SSI_RXD TSCKP=1, RSCKP=1 Figure 27-32. Internal Gated Mode Timing - Falling Edge Clocking/Rising Edge Latching SSI_BCLK SSI_TXD SSI_RXD TSCKP=0, RSCKP=0 Figure 27-33. External Gated Mode Timing - Rising Edge Clocking/Falling Edge Latching 27-42 Freescale Semiconductor...
Page 710 S master mode S slave mode Normal mode In normal (non-I S) mode operation, no register bits are forced to any particular state internally, and the user can program the SSI to work in any operating condition. Freescale Semiconductor 27-43...
Page 711 27.4.1.4.2 S Slave Mode In I S slave mode (SSI_CR[I2S] = 10), the following additional settings are recommended: • External generated bit clock (SSI_TCR[TXDIR] = 0) • External generated frame sync (SSI_TCR[TFDIR] = 0) 27-44 Freescale Semiconductor...
Page 712 Rx frame sync is active high (SSI_RCR[RFSI] = 0) • Tx frame sync length is one-word-long-frame (SSI_TCR[TFSL] = 0) • Rx frame sync length is one-word-long-frame (SSI_RCR[RFSL] = 0) • Tx frame sync initiated one bit before data is transmitted (SSI_TCR[TEFS] = 1) Freescale Semiconductor 27-45...
Page 713 SSI should be idle, after operating for one frame. The following shows the slot assignments in a valid transmit frame: • Slot 0: The tag value (written by the user program) • Slot 1: If RD/WR command, command address 27-46 Freescale Semiconductor...
Page 714: Ssi Clocking
In master mode, the SSI_MCLK signal is the serial master clock if enabled by the SSI_CR[MCE] bit. This serial master clock is an oversampling clock of the frame sync clock (SSI_FS). In this mode, the word length (WL), prescaler range Freescale Semiconductor 27-47...
Page 715 When internally generated, receive and transmit frame sync generate from the word clock and are defined by the frame rate divider (DC) bits and the word length (WL) bits of the SSI_CCR. 27-48 Freescale Semiconductor...
Page 716 Table 27-26. SSI Bit Clock and Frame Rate as a Function of PSR, PM, and DIV2 SSI_CLKIN SSI_CCR Bit Clk (kHz) Frame rate freq (MHz) SSI_BCLK (kHz) (SSI_MCLK) DIV2 PSR 12.288 12.288 Freescale Semiconductor 27-49...
Page 717: External Frame And Clock Operation
Therefore, data can appear in different places in SSI_TX0/1 and SSI_RX0/1 based on the data format and the number of bits per word. Independent data formats are supported for the transmitter and receiver (i.e. the transmitter and receiver can use different data formats). 27-50 Freescale Semiconductor...
Page 718 • In sign-extension, all bits above the most significant bit are equal to the most significant bit. This format is useful when data is stored in a fixed-point integer format (which implies fractional values). Freescale Semiconductor 27-51...
Page 719: Receive Interrupt Enable Bit Description
Tx FIFO 1). If not enabled, then one value can be written to the SSI_TX0 register (one per channel in two-channel mode using SSI_TX1). When the TIE bit is cleared, all transmit interrupts are disabled. However, the TDE0/1 bits always indicate the corresponding SSI_TX register 27-52 Freescale Semiconductor...
Page 720: Initialization/Application Information
To ensure proper operation of the SSI, use the power-on or SSI reset before changing any of the control bits listed in Table 27-31. NOTE These control bits should not be changed when the SSI module is enabled. Freescale Semiconductor 27-53...
Page 721 SSI_IER [20]=TDMAE [9]=RXBIT0 and TXBIT0 [8]=RFEN1 and TFEN1 [7]=RFEN0 and TFEN0 [6]=TFDIR SSI_RCR [5]=RXDIR and TXDIR SSI_TCR [4]=RSHFD and TSHFD [3]=RSCKP and TSCKP [2]=RFSI and TFSI [1]=RFSL and TFSL [0]=REFS and TEFS SSI_CCR [16:13]=WL [1]=FV SSI_ACR [10:5]=FRDIV 27-54 Freescale Semiconductor...
Page 722: Introduction
Figure 28-1. Real Time Clock Block Diagram 28.1.1 Overview This section discusses how to operate and program the real-time clock (RTC) module that maintains a time-of-day clock, provides stopwatch, alarm, and interrupt functions, and supports the following features. Freescale Semiconductor 28-1...
Page 723: Features
Table 28-15 lists some examples of the interrupt frequencies of the sampling timer for the possible reference clocks. Sampling frequencies are dependent upon the RTC oscillator frequency and the value in RTC_GOC[31:9]. • Minute Stopwatch 28-2 Freescale Semiconductor...
Page 724: External Signal Description
This register programs the hours and minutes for the TOD clock. It can be read or written at any time. After a write, the time changes to the new value. This register cannot be reset because the real-time clock is always enabled at reset. Freescale Semiconductor 28-3...
Page 725: Rtc Seconds Counter Register (Rtc_Seconds)
Current seconds. Set to any value between 0 and 59 (0x3B). SECONDS 28.3.3 RTC Hours and Minutes Alarm Register (RTC_ALRM_HM) The RTC_ALRM_HM register configures the hours and minutes setting for the alarm. The alarm settings can be read or written at any time. 28-4 Freescale Semiconductor...
Page 726: Rtc Seconds Alarm Register (Rtc_Alrm_Sec)
Description 31–6 Reserved, must be cleared. 5–0 Seconds setting of the alarm. The value written to this field must be the alarm time desired minus one second. Set SECONDS to any value between 0 and 59 (0x3B). Freescale Semiconductor 28-5...
Page 727: Rtc Control Register (Rtc_Cr)
Interrupts may occur while the system clock is idle or in sleep mode. Address: 0xFC03_C014 (RTC_ISR) Access: User read/write Reset R SAM7 SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0 2HZ W w1c Reset Figure 28-7. RTC Interrupt Status Register (RTC_ISR) 28-6 Freescale Semiconductor...
Page 728: Rtc Interrupt Enable Register (Rtc_Ier)
0 The stopwatch did not timeout 1 The stopwatch timed out 28.3.7 RTC Interrupt Enable Register (RTC_IER) The RTC_IER register enables/disables the various real-time clock interrupts. Masking an interrupt bit has no effect on its corresponding status bit. Freescale Semiconductor 28-7...
Page 729 0 Interrupt disable 1 Stopwatch interrupt enabled. The stopwatch counts down and remains at -1 (0x3F) until it is reprogrammed. If this bit is enabled with RTC_STPWCF equal to 0x3F, an interrupt is requested on the next minute tick. 28-8 Freescale Semiconductor...
Page 730: Rtc Stopwatch Minutes Register (Rtc_Stpwch)
Current day count. Set to any value between 0 and 65,535 (0xFFFF). DAYS 28.3.10 RTC Day Alarm Register (RTC_ALRM_DAY) The RTC_ALRM_DAY register configures the day for the alarm. The alarm settings can be read or written at any time. Freescale Semiconductor 28-9...
Page 731: Rtc General Oscillator Clock Upper Register (Rtc_Gocu)
RTC oscillator clock to create a 1 Hz and sample frequencies. This register can be read or written at any time. A non-zero value must be programmed into RTC_GOC for the 1 Hz internal clock to function. 28-10 Freescale Semiconductor...
Page 732: Functional Description
1HZ interrupt flag to set. When the seconds counter rolls from 59 to 00, the minute counter increments and the MIN interrupt flag is set. The same is true for the minute counter with the HR signal and the hour counter with the DAY signal. Freescale Semiconductor 28-11...
Page 733: Alarm
32.00 Hz 32.26Hz SAM2 16.13 Hz 16.00 Hz 16.00 Hz 16.13 SAM1 8.06 Hz 8.00 Hz 8.00 Hz 8.06 Hz SAM0 4.03 Hz 4.00 Hz 4.00 Hz 4.03 Hz 2.02 Hz 2.00 Hz 2.00 Hz 2.02 Hz 28-12 Freescale Semiconductor...
Page 734: Minute Stopwatch
Configure RTC_IER Check RTC_ISR Figure 28-14. Flow Chart of RTC Operation 28.5.2 Programming the Alarm or Time-of-Day Registers Use the following procedure illustrated in Figure 28-15 when changing the alarm or time-of-day (day, hour, minute, and second) registers. Freescale Semiconductor 28-13...
Page 735 Disable the alarm interrupt (clear RTC_IER[ALM]) Program the alarm or time-of-day registers Clear any incidental alarm interrupt during programming (write 1 to RTC_ISR[ALM]) Enable the alarm interrupt (set RTC_IER[ALM] Figure 28-15. Flow Chart of Alarm and Time-of-Day Programming 28-14 Freescale Semiconductor...
Page 736: Introduction
This subsection describes the operation of the PIT modules in low-power modes and debug mode of operation. Low-power modes are described in the power management module, Chapter 9, “Power Management.” Table 29-1 shows the PIT module operation in low-power modes and how it can exit from each mode. Freescale Semiconductor 29-1...
Page 737: Memory Map/Register Definition
Table 29-2. Programmable Interrupt Timer Modules Memory Map Address PIT 0 Width Register Access Reset Value Section/Page PIT 1 (bits) PIT 2 PIT 3 Supervisor Access Only Registers 0xFC08_0000 PIT Control and Status Register (PCSRn) 0x0000 29.2.1/29-3 0xFC08_4000 0xFC08_8000 0xFC08_C000 29-2 Freescale Semiconductor...
Page 738: Pit Control And Status Register (Pcsrn)
User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 29.2.1 PIT Control and Status Register (PCSRn) The PCSRn registers configure the corresponding timer’s operation. Address: 0xFC08_0000 (PCSR0) Access: Supervisor 0xFC08_4000 (PCSR1) read/write 0xFC08_8000 (PCSR2) 0xFC08_C000 (PCSR3) DOZE DBG OVW Reset Figure 29-2. PCSRn Register Freescale Semiconductor 29-3...
Page 739 PIT interrupt flag. This read/write bit is set when PIT counter reaches 0x0000. Clear PIF by writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears PIF. 0 PIT count has not reached 0x0000. 1 PIT count has reached 0x0000. 29-4 Freescale Semiconductor...
Page 740: Pit Modulus Register (Pmrn)
29.2.3 PIT Count Register (PCNTRn) The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two 8-bit reads is not guaranteed coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally. Freescale Semiconductor 29-5...
Page 741: Functional Description
0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement. When the counter reaches a count of 0x0000, PCSRn[PIF] flag is set. If the PCSRn[PIE] bit is set, PIF flag issues an interrupt request to the CPU. 29-6 Freescale Semiconductor...
Page 742: Timeout Specifications
Timeout The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR. Freescale Semiconductor 29-7...
Page 743: Introduction
DMA transfer on a particular event. NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 16, “Pin Multiplexing and Control”) prior to configuring the DMA Timers. Freescale Semiconductor 30-1...
Page 744: Features
Programmable mode for the output pin on reference compare • Free run and restart modes • Programmable interrupt or DMA request on input capture or reference-compare • Ability to stop the timer from counting when the ColdFire core is halted Freescale Semiconductor 30-2...
Page 745: Memory Map/Register Definition
0xFC07_800C 0xFC07_C00C 30.2.1 DMA Timer Mode Registers (DTMRn) The DTMRn registers program the prescaler and various timer modes. Address: 0xFC07_0000 (DTMR0) Access: User read/write 0xFC07_4000 (DTMR1) 0xFC07_8000 (DTMR2) 0xFC07_C000 (DTMR3) ORRI FRR Reset Figure 30-2. DTMRn Registers 30-3 Freescale Semiconductor...
Page 746 Reset timer. Performs a software timer reset similar to an external reset, although other register values can be written while RST is cleared. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked unless the timer is enabled. 0 Reset timer (software reset) 1 Enable timer Freescale Semiconductor 30-4...
Page 747: Dma Timer Extended Mode Registers (Dtxmrn)
If configured to generate a DMA request, processing of the DMA data transfer automatically clears the REF and CAP flags via the internal DMA ACK signal. 30-5 Freescale Semiconductor...
Page 748 Capture on rising edge and trigger interrupt Capture on rising edge and trigger DMA Capture on falling edge and trigger interrupt Capture on falling edge and trigger DMA Capture on any edge and trigger interrupt Capture on any edge and trigger DMA Freescale Semiconductor 30-6...
Page 749: Dma Timer Reference Registers (Dtrrn)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30-6. DTCRn Registers Table 30-6. DTCRn Field Descriptions Field Description 31–0 Captures the corresponding DTCNn value during a capture operation when an edge occurs on DTnIN, as programmed in DTMRn. 30-7 Freescale Semiconductor...
Page 750: Capture Mode
Each DMA timer can be configured to count up to a reference value. If the reference value is met, DTERn[REF] is set. • If DTMRn[ORRI] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted. • If DTMRn[ORRI] and DTXMRn[DMAEN] are set, a DMA request is asserted. Freescale Semiconductor 30-8...
Page 751: Output Mode
DTCN0 EQU 0xFC07_000C ;Timer0 counter register DTCN1 EQU 0xFC07_400C ;Timer1 counter register DTER0 EQU 0xFC07_0003 ;Timer0 event register DTER1 EQU 0xFC07_4003 ;Timer1 event register * TMR0 is defined as: * *[PS] = 0xFF, divide clock by 256 30-9 Freescale Semiconductor...
Page 752: Calculating Time-Out Values
1 or 16 DTMRn[PS] DTRRn[REF] Eqn. 30-1 When calculating time-out periods, add one to the prescaler to simplify calculating, because DTMRn[PS] equal to 0x00 yields a prescaler of one, and DTMRn[PS] equal to 0xFF yields a prescaler of 256. Freescale Semiconductor 30-10...
Page 753 For example, if a 133-MHz timer clock is divided by 16, DTMRn[PS] equals 0x7F, and the timer is referenced at 0x1FB5B (129,883 decimal), the time-out period is:        Timeout period 129883 2.00 seconds ---------------------- - Eqn. 30-2  30-11 Freescale Semiconductor...
Page 754: Introduction
The DMA serial peripheral interface (DSPI) block provides a synchronous serial bus for communication between an MCU and an external peripheral device. The DSPI supports up to 32 queued SPI transfers (16 receive and 16 transmit) in the DSPI resident FIFOs eliminating CPU intervention between transfers. Freescale Semiconductor 31-1...
Page 755: Features
– FIFO underflow (slave only, the slave is asked to transfer data when the TX FIFO is empty) (TFUF) – RX FIFO is not empty (RFDF) – FIFO overflow (attempt to transmit with an empty TX FIFO or serial frame received while RX FIFO is full) (RFOF) 31-2 Freescale Semiconductor...
Page 756: Modes Of Operation
DSPI stops while in module disable mode. The DSPI enters the module disable mode when the DSPI_MCR[MDIS] bit is set. See Section 31.4.7, “Power Saving Features,” for more details on the module disable mode. Freescale Semiconductor 31-3...
Page 757: External Signal Description
Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPI_PCS5/PCSS) When the DSPI is in master mode and the DSPI_MCR[PCSSE] bit is cleared, DSPI_PCS5 selects the slave device for which the current transfer is intended. DSPI_PCS5 is a peripheral select output signal. 31-4 Freescale Semiconductor...
Page 758: Serial Input (Dspi_Sin)
The DSPI_MCR contains bits that configure various attributes associated with DSPI operation. The HALT and MDIS bits can be changed at any time, but only take effect on the next frame boundary. Only the HALT and MDIS bits in the DSPI_MCR may be changed while the DSPI is running. Freescale Semiconductor 31-5...
Page 759 Modified timing format enable. Enables a modified transfer format to be used. See Section 31.4.4.4, “Modified SPI MTFE Transfer Format (MTFE = 1, CPHA = 1),” for more information. 0 Modified SPI transfer format disabled 1 Modified SPI transfer format enabled 31-6 Freescale Semiconductor...
Page 760 SIN pin. 00 0 system clocks between DSPI_SCK edge and DSPI_SIN sample 01 1 system clock between DSPI_SCK edge and DSPI_SIN sample 10 2 system clocks between DSPI_SCK edge and DSPI_SIN sample 11 Reserved Freescale Semiconductor 31-7...
Page 761: Dspi Transfer Count Register (Dspi_Tcr)
DSPI_CTARs support compatibility with the QSPI module in the ColdFire family of MCUs. At the initiation of an SPI transfer, control logic selects the DSPI_CTAR that contains the transfer’s attributes. Do not write to the DSPI_CTARs while the DSPI is running. 31-8 Freescale Semiconductor...
Page 762 0xFC05_C00C (DSPI_CTAR0) Access: User read/write 0xFC05_C010 (DSPI_CTAR1) 0xFC05_C014 (DSPI_CTAR2) 0xFC05_C018 (DSPI_CTAR3) 0xFC05_C01C (DSPI_CTAR4) 0xFC05_C020 (DSPI_CTAR5) 0xFC05_C024 (DSPI_CTAR6) 0xFC05_C028 (DSPI_CTAR7) FMSZ CPOL CPHA PCSSCK PASC Reset CSSCK Reset Figure 31-4. DSPI Clock and Transfer Attributes Registers 0–7 (DSPI_CTARn) Freescale Semiconductor 31-9...
Page 763 Frame size. Selects the number of bits transferred per frame. The FMSZ field is used in master mode and slave FMSZ mode. The table below lists the frame sizes. FMSZ Framesize FMSZ Framesize 0000 Reserved 1000 0001 Reserved 1001 0010 Reserved 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 31-10 Freescale Semiconductor...
Page 764 01 3 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler 10 5 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler 11 7 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler Freescale Semiconductor 31-11...
Page 765 1024 0010 1010 2048 0011 1011 4096 0100 1100 8192 0101 1101 16384 0110 1110 32768 0111 1111 65536 Note: See Section 31.4.3.2, “PCS to SCK Delay (tCSC),” for details on calculating the PCS to SCK delay. 31-12 Freescale Semiconductor...
Page 766 1001 1024 0010 1010 2048 0011 1011 4096 0100 1100 8192 0101 1101 16384 0110 1110 32768 0111 1111 65536 Note: See Section 31.4.3.4, “Delay after Transfer (tDT),” for more details on calculating the delay after transfer. Freescale Semiconductor 31-13...
Page 767: Dspi Status Register (Dspi_Sr)
DSPI_SR by writing a 1 to it. Writing a 0 to a flag bit has no effect. Address 0xFC05_C02C (DSPI_SR) Access: User Read/Write R TCF TXRXS EOQF TFUF TFFF RFOF RFDF W w1c Reset TXCTR TXNXTPTR RXCTR POPNXTPTR Reset Figure 31-5. DSPI Status Register (DSPI_SR) 31-14 Freescale Semiconductor...
Page 768 1 to it or by an acknowledgement from the eDMA controller when the RX FIFO is empty. 0 RX FIFO is empty 1 RX FIFO is not empty Note: In the interrupt service routine, RFDF must be cleared only after the DSPI_POPR register is read. Reserved, must be cleared. Freescale Semiconductor 31-15...
Page 769: Dspi Dma/Interrupt Request Select And Enable Register (Dspi_Rser)
Table 31-7. DSPI_RSER Field Descriptions Field Description Transmission complete request enable. Enables DSPI_SR[TCF] flag to generate an interrupt request. TCF_RE 0 TCF interrupt requests are disabled 1 TCF interrupt requests are enabled 30–29 Reserved, must be cleared. 31-16 Freescale Semiconductor...
Page 770: Dspi Push Transmit Fifo Register (Dspi_Pushr)
TX FIFO. See Section 31.4.2.4, “TX FIFO Buffering Mechanism,” for more information. Write accesses of 8- or 16-bits to the DSPI_PUSHR transfer 32 bits to the TX FIFO. NOTE Only the TXDATA field is used for DSPI slaves. Freescale Semiconductor 31-17...
Page 771 DSPI_TCR[SPI_TCNT] field. The SPI_TCNT field is cleared before transmission of the current SPI frame begins. This bit is used only in SPI master mode. 0 Do not clear DSPI_TCR[SPI_TCNT] field 1 Clear DSPI_TCR[SPI_TCNT] field 25–24 Reserved, must be cleared. 31-18 Freescale Semiconductor...
Page 772: Dspi Pop Receive Fifo Register (Dspi_Popr)
The DSPI_TXFRn registers provide visibility into TX FIFO for debugging purposes. Each register is an entry in TX FIFO. The registers are read-only and cannot be modified. Reading the DSPI_TXFRn registers does not alter the state of TX FIFO. The 16-entry deep FIFO is implemented with 16 registers, DSPI_TXFR0–15. Freescale Semiconductor 31-19...
Page 773: Dspi Receive Fifo Registers 0–15 (Dspi_Rxfrn)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RXDATA Reset 0 Figure 31-10. DSPI Receive FIFO Registers (DSPI_RXFRn) Table 31-11. DSPI_RXFRn Field Description Field Description 31–16 Reserved, must be cleared. 15–0 Receive data. Contains the received SPI data. RXDATA 31-20 Freescale Semiconductor...
Page 774: Start And Stop Of Dspi Transfers
(DSPI_MCR[HALT] is set). The DSPI_SR[TXRXS] bit is cleared in this state. In the running state, serial transfers take place. The DSPI_SR[TXRXS] bit is set in the running state. Figure 31-12 shows a state diagram of the start and stop mechanism. The transitions are described in Table 31-12. Freescale Semiconductor 31-21...
Page 775: Serial Peripheral Interface (Spi) Configuration
DSPI, and the SPI command field of the TX FIFO entry is ignored. For information on switching between master and slave modes see Section 31.5.2, “Switching Master and Slave Mode.” 31-22 Freescale Semiconductor...
Page 776 TX FIFO by writing to the DSPI push TX FIFO register (DSPI_PUSHR). For more information on DSPI_PUSHR, refer to Section 31.3.6, “DSPI Push Transmit FIFO Register (DSPI_PUSHR).” TX FIFO entries can only be removed from the TX FIFO by being shifted out or by flushing the TX FIFO. Freescale Semiconductor 31-23...
Page 777 The RXCTR is updated every time the DSPI _POPR is read or SPI data is copied from the shift register to the RX FIFO. The DSPI_SR[POPNXTPTR] field points to the RX FIFO entry returned when the DSPI_POPR is read. The POPNXTPTR contains the positive, 32-bit word offset from DSPI_RXFR0. For example, 31-24 Freescale Semiconductor...
Page 778: Dspi Baud Rate And Clock Delay Generation
DSPI_CTARn[BR]) to produce DSPI_SCK with the possibility of doubling the baud rate. The DBR, PBR, and BR fields in the DSPI_CTARn select the frequency of DSPI_SCK using the following formula: SYS/2  Eqn. 31-1 SCK baud rate ------------------------------------------------- - --------------------------------------- - PBR Prescaler Value BR Scaler Value Freescale Semiconductor 31-25...
Page 779 DSPI_PCS signal for the next frame. See Figure 31-15 for an illustration of the delay after transfer. DSPI_CTARn[PDT, DT] fields select the delay after transfer by the formula:   ------------ - Eqn. 31-4 SYS/2 31-26 Freescale Semiconductor...
Page 780 SYS/2 0b11 100 MHz 70.0 ns Table 31-18 shows an example of the computed t delay PASC Table 31-18. Peripheral Chip Select Strobe Negate Computation Example PASC Prescaler Delay after Transfer SYS/2 0b11 100 MHz 70.0 ns Freescale Semiconductor 31-27...
Page 781: Transfer Formats
In this format, the master and slave sample their DSPI_SIN pins on the odd-numbered DSPI_SCK edges and change the data on their DSPI_SOUT pins on the even-numbered DSPI_SCK edges. 31-28 Freescale Semiconductor...
Page 782 DSPI_SCK edge before the first data bit becomes available on the slave DSPI_SOUT pin. In this format, the master and slave devices change the data on their DSPI_SOUT pins on the odd-numbered DSPI_SCK edges and sample the data on their DSPI_SIN pins on the even-numbered DSPI_SCK edges. Freescale Semiconductor 31-29...
Page 783 In this modified transfer format, the master and the slave sample later in the DSPI_SCK period than in classic SPI mode to allow for delays in device pads and board traces. These delays become a more significant fraction of the DSPI_SCK period as the DSPI_SCK period decreases with increasing baud rates. 31-30 Freescale Semiconductor...
Page 784 Slave Sample Master Sample Slave DSPI_SOUT Master DSPI_SOUT DSPI_PCSn System Clock System Clock = PCS to SCK delay. = After SCK delay. Figure 31-17. DSPI Modified Transfer Format (MTFE = 1, CPHA = 0, Fsck = Fsys/4) Freescale Semiconductor 31-31...
Page 785 When CONT is cleared, DSPI drives the asserted chip select signals to their idle states in between frames. The idle states of the chip select signals are selected by the DSPI_MCR[PCSIS] field. Figure 31-19 shows the timing diagram for two four-bit transfers with CPHA set and CONT cleared. 31-32 Freescale Semiconductor...
Page 786 The DSPI_PCSn signal must be negated before DSPI_CTAR is switched. When CONT is set and the DSPI_PCSn signals for the next transfer are different from the present transfer, the DSPI_PCSn signals behave as if the CONT bit was cleared. Freescale Semiconductor 31-33...
Page 787: Continuous Serial Communications Clock
Enabling continuous SCK disables the PCS to SCK delay and the after SCK delay. The delay after transfer is fixed at one DSPI_SCK cycle. Figure 31-22 shows timing diagram for continuous SCK format with continuous selection disabled. 31-34 Freescale Semiconductor...
Page 788: Interrupts/Dma Requests
End of transfer queue has been reached (EOQ) EOQF — TX FIFO is not full TFFF Current frame transfer is complete — TX FIFO underflow has occurred TFUF — RX FIFO is not empty RFDF RX FIFO overflow has occurred RFOF — Freescale Semiconductor 31-35...
Page 789 TX FIFO of a DSPI operating in slave mode is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while the DSPI_RSER[TFUF_RE] bit is set, an interrupt request is generated. 31-36 Freescale Semiconductor...
Page 790: Power Saving Features
31.4.7.2 Slave Interface Signal Gating The DSPI’s module enable signal gates slave interface signals such as address, byte enable, read/write and data. This prevents toggling slave interface signals from consuming power unless the DSPI is accessed. Freescale Semiconductor 31-37...
Page 791: How To Change Queues
Baud Rate Settings Table 31-21 shows the baud rate generated based on the combination of the baud rate prescaler PBR and the baud rate scaler BR in the DSPI_CTARn registers. The values calculated assume a 100 MHz system frequency. 31-38 Freescale Semiconductor...
Page 792: Delay Settings
(t ) and CS to SCK delay (t ) that can be generated based on the prescaler values and the scaler values set in the DSPI_CTARn registers. The values calculated assume a 100 MHz system frequency. Freescale Semiconductor 31-39...
Page 793: Calculation Of Fifo Pointer Addresses
FIFO entries along with the FIFO counter. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO. See Section 31.4.2.4, “TX FIFO Buffering Mechanism,” Section 31.4.2.5, “RX FIFO Buffering Mechanism,” for details on the FIFO operation. 31-40 Freescale Semiconductor...
Page 794 Last-in entry address = RX FIFO base + 4  [(RXCTR + POPNXTPTR - 1) modulo RX FIFO depth] RX FIFO base: base address of RX FIFO RXCTR: RX FIFO counter POPNXTPTR: pop next pointer RX FIFO depth: 16 Freescale Semiconductor 31-41...
Page 795: Introduction
Interrupt Request Interrupt Control (to Interrupt Controller) Logic Programmable Internal Bus Clock (f Clock Transmit DMA Request sys/2 DMA Request Generation or External Clock (DTnIN) Logic Receive DMA Request (To DMA Controller) Figure 32-1. UART Block Diagram Freescale Semiconductor 32-1...
Page 796: Features
Four maskable interrupt conditions • All three UARTs have DMA request capability • Parity, framing, and overrun error detection • False-start bit detection • Line-break detection and generation • Detection of breaks originating in the middle of a character Freescale Semiconductor 32-2...
Page 797: External Signal Description
Writing control bytes into the appropriate registers controls the operation of the UART module. NOTE UART registers are accessible only as bytes. NOTE Interrupt can mean an interrupt request asserted to the CPU or a DMA request. 32-3 Freescale Semiconductor...
Page 798 UMR1n, UMR2n, and UCSRn must be changed only after the receiver/transmitter is issued a software reset command. If operation is not disabled, undesirable results may occur. Reading this register results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed. Freescale Semiconductor 32-4...
Page 799: Uart Mode Registers 1 (Umr1N)
Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below. 32-5 Freescale Semiconductor...
Page 800: Uart Mode Register 2 (Umr2N)
UMR1n. UMR2n accesses do not update the pointer. Address: 0xFC06_0000 (UMR20) Access: User read/write 0xFC06_4000 (UMR21) 0xFC06_8000 (UMR22) TXRTS TXCTS Reset: After UMR1n is read or written, the pointer points to UMR2n Figure 32-4. UART Mode Registers 2 (UMR2n) Freescale Semiconductor 32-6...
Page 801 1000 1.563 0001 1.125 0.625 1001 1.625 0010 1.188 0.688 1010 1.688 0011 1.250 0.750 1011 1.750 0100 1.313 0.813 1100 1.813 0101 1.375 0.875 1101 1.875 0110 1.438 0.938 1110 1.938 0111 1.500 1.000 1111 2.000 32-7 Freescale Semiconductor...
Page 802: Uart Status Registers (Usrn)
1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded into the transmitter holding register are not sent. Freescale Semiconductor 32-8...
Page 803: Uart Clock Select Registers (Ucsrn)
UART Command Registers (UCRn) The UCRs supply commands to the UART. Only multiple commands that do not conflict can be specified in a single write to a UCRn. For example, cannot be RESET TRANSMITTER ENABLE TRANSMITTER specified in one command. 32-9 Freescale Semiconductor...
Page 804 Transmitter must be enabled for the command to be accepted. This command ignores the state of UnCTS. Causes UnTXD to go high (mark) within two bit times. Any characters in the STOP BREAK transmit buffer are sent. Freescale Semiconductor 32-10...
Page 805: Uart Receive Buffers (Urbn)
FIFO. UnRXD is connected to the serial shift register. The CPU reads from the top of the FIFO while the receiver shifts and updates from the bottom when the shift register is full (see Figure 32-18). RB contains the character in the receiver. 32-11 Freescale Semiconductor...
Page 806: Uart Transmit Buffers (Utbn)
UART Input Port Change Registers (UIPCRn) The UIPCRs hold the current state and the change-of-state for UnCTS. Address: 0xFC06_0010 (UIPCR0) Access: User read-only 0xFC06_4010 (UIPCR1) 0xFC06_8010 (UIPCR2) Reset: UnCTS Figure 32-10. UART Input Port Changed Registers (UIPCRn) Freescale Semiconductor 32-12...
Page 807: Uart Auxiliary Control Register (Uacrn)
UISRn bit has no effect on the output. The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user with interrupt status, while writing controls the mask bits. 32-13 Freescale Semiconductor...
Page 808 0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the transmitter holding register when TXRDY is cleared are not sent. 1 The transmitter holding register is empty and ready to be loaded with a character. Freescale Semiconductor 32-14...
Page 809: Uart Baud Rate Generator Registers (Ubg1N/Ubg2N)
CPU. 32.3.12 UART Input Port Register (UIPn) The UIPn registers show the current state of the UnCTS input. Address: 0xFC06_0034 (UIP0) Access: User read-only 0xFC06_4034 (UIP1) 0xFC06_8034 (UIP2) Reset: Figure 32-15. UART Input Port Registers (UIPn) 32-15 Freescale Semiconductor...
Page 810: Uart Output Port Command Registers (Uop1N/Uop0N)
The internal bus clock serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each UART. The 16-bit divider is used to produce standard UART baud rates. Freescale Semiconductor 32-16...
Page 811 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate calculation is: Using a 133-MHz internal bus clock and letting baud rate equal 9600, then 133MHz     Divider ------------------------------ - 433 decimal 0x01B0 hexadecimal Eqn. 32-1   32 x 9600 32-17 Freescale Semiconductor...
Page 812: Transmitter And Receiver Operating Modes
After the stop bits are sent, if no new character is in the transmitter holding register, the UnTXD output remains high (mark condition) and the transmitter empty bit (USRn[TXEMP]) is set. Transmission Freescale Semiconductor 32-18...
Page 813 Transmitter Enabled USRn[TXRDY] internal module select Start C4 Stop break break transmitted UnCTS Manually asserted Manually UnRTS command asserted Cn = transmit characters W = write UMR2n[TXCTS] = 1 UMR2n[TXRTS] = 1 Figure 32-19. Transmitter Timing Diagram 32-19 Freescale Semiconductor...
Page 814 The receiver places the damaged character in the Rx FIFO and sets the corresponding USRn error bits and USRn[RXRDY]. Then, if the break lasts until the next character time, the receiver places an all-zero character into the Rx FIFO and sets USRn[RB,RXRDY]. Figure 32-20 shows receiver functional timing. Freescale Semiconductor 32-20...
Page 815 FFULL bit can be selected to cause an interrupt and TXRDY or RXRDY can be used to generate a DMA request. The two error modes are selected by UMR1n[ERR]: • In character mode (UMR1n[ERR] = 0), status is given in the USRn for the character at the top of the FIFO. 32-21 Freescale Semiconductor...
Page 816: Looping Modes
In this mode, received data is clocked on the receiver clock and re-sent on UnTXD. The receiver must be enabled, but the transmitter need not be. UnRXD Input UnRXD Input Disabled Disabled UnTXD Output Figure 32-21. Automatic Echo Freescale Semiconductor 32-22...
Page 817: Multidrop Mode
Setting UMR1n[PM] programs the UART to operate in a wake-up mode for multidrop or multiprocessor applications. In this mode, a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations. 32-23 Freescale Semiconductor...
Page 818 If the receiver is disabled, it sets the RXRDY bit and loads the character into the receiver holding register FIFO provided the received A/D bit is a 1 (address tag). The character is Freescale Semiconductor 32-24...
Page 819: Bus Operation
UART module generates an interrupt caused by a change-in-break (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 32-25 Freescale Semiconductor...
Page 820: Interrupt And Dma Request Initialization
UART, the DMA would typically generate an end-of-data-transfer interrupt request to the CPU. The resulting interrupt service routine (ISR) should query the UART programming model to determine the end-of-transmission status. In typical applications, the receive DMA request Freescale Semiconductor 32-26...
Page 821: Uart Module Initialization Sequence
Select the mode of operation (CM bits). b) If preferred, program operation of transmitter ready-to-send (TXRTS). c) If preferred, program operation of clear-to-send (TXCTS bit). d) Select stop-bit length (SB bits). 7. UCRn: Enable transmitter and/or receiver. 32-27 Freescale Semiconductor...
Page 822 UART Modules Enable Serial Module Errors? SINIT Initiate: Channel Enable Receiver Interrupts CHK1 Assert Request To Send Call CHCHK SINITR Return Save Channel Status Figure 32-25. UART Mode Programming Flowchart (Sheet 1 of 5) Freescale Semiconductor 32-28...
Page 823 Status Word TxCHK Set Transmitter- Waited Transmitter Never-ready Flag Too Long? Ready? SNDCHR Send Character To Transmitter RxCHK Waited Set Receiver- Character Been Too Long? Never-ready Flag Received? Figure 32-25. UART Mode Programming Flowchart (Sheet 2 of 5) 32-29 Freescale Semiconductor...
Page 824 Error Flag To Original Mode PRCHK Have Return Parity Error? Set Parity Error Flag CHRCHK Get Character From Receiver Same As Transmitted Character? Set Incorrect Character Flag Figure 32-25. UART Mode Programming Flowchart (Sheet 3 of 5) Freescale Semiconductor 32-30...
Page 825 Return IRQ Arrived Yet? Clear Change-in- Break Status Bit Remove Break Character From Receiver FIFO Replace Return Address On System Stack And Monitor Warm Start Address SIRQR Figure 32-25. UART Mode Programming Flowchart (Sheet 4 of 5) 32-31 Freescale Semiconductor...
Page 826 UART Modules OUTCH Transmitter Ready? Send Character To Transmitter Return Figure 32-25. UART Mode Programming Flowchart (Sheet 5 of 5) Freescale Semiconductor 32-32...
Page 827: Introduction
C Address Divider Register Register Register I/O Register Register (I2FDR) (I2CR) (I2SR) (I2DR) (I2ADR) In/Out Clock Data Control Shift Register Start, Stop, Arbitration Control Input Address Sync Compare I2C_SCL I2C_SDA Figure 33-1. I C Module Block Diagram Freescale Semiconductor 33-1...
Page 828: Overview
Interrupt-driven, byte-by-byte data transfer • Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation/detection • Repeated START signal generation • Acknowledge bit generation/detection • Bus-busy detection Freescale Semiconductor 33-2...
Page 829: Memory Map/Register Definition
C Frequency Divider Register (I2FDR) The I2FDR, shown in Figure 33-3, provides a programmable prescaler to configure the I C clock for bit-rate selection. Address: 0xFC05_8004 (I2FDR) Access: User read/write Reset: Figure 33-3. I C Frequency Divider Register (I2FDR) 33-3 Freescale Semiconductor...
Page 830 C module and the I C interrupt. It also contains bits that govern operation as a slave or a master. Address: 0xFC05_8008 (I2CR) Access: User read/write IIEN MSTA TXAK RSTA Reset: Figure 33-4. I C Control Register (I2CR) Freescale Semiconductor 33-4...
Page 831 1 Generates a repeated START condition. 1–0 Reserved, must be cleared. 33.2.4 C Status Register (I2SR) I2SR contains bits that indicate transaction direction and status. Address: 0xFC05_800C (I2SR) Access: User read/write IAAS RXAK Reset: Figure 33-5. I C Status Register (I2SR) 33-5 Freescale Semiconductor...
Page 832 C Data I/O Register (I2DR) In master-receive mode, reading I2DR allows a read to occur and for the next data byte to be received. In slave mode, the same function is available after the I C has received its slave address. Freescale Semiconductor 33-6...
Page 833: Start Signal
33-7). A START signal is defined as a high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves. 33-7 Freescale Semiconductor...
Page 834: Slave Address Transmission
Interrupt Bit Set (Byte Complete) I2C_SDA Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Slave Address Data Byte STOP ACK from START ACK Bit Signal Receiver Signal Figure 33-8. Data Transfer Freescale Semiconductor 33-8...
Page 835: Stop Signal
A repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication, as shown in Figure 33-10. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 33-9 Freescale Semiconductor...
Page 836 7bit Slave Address Data Note: No acknowledge on the last byte Example 3: 7-bit Slave Rept 7-bit Slave Data Data Data Address Address Master Writes to Slave Master Reads from Slave Figure 33-11. Data Transfer, Combined Format Freescale Semiconductor 33-10...
Page 837: Clock Synchronization And Arbitration
STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration. I2C_SCL I2C_SDA by Master1 I2C_SDA by Master 2 Loses Arbitration, Master2 and becomes slave-receiver I2C_SDA Figure 33-13. Arbitration Procedure 33-11 Freescale Semiconductor...
Page 838: Handshaking And Clock Stretching
The free time between a STOP and the next START condition is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the I2C_SCL period, the Freescale Semiconductor 33-12...
Page 839: Generation Of Stop
2. Get value from transmitting counter, TXCNT. If no more data, go to step #5. 3. Transmit next byte of data via I2DR. 4. Decrement TXCNT and go to step #1 5. Generate a stop condition by clearing I2CR[MSTA]. 33-13 Freescale Semiconductor...
Page 840: Generation Of Repeated Start
MSTA without signaling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, slave service routine should first test IAL and software should clear it if it is set. Freescale Semiconductor 33-14...
Page 841 Set RX Rx Mode Rx Mode Mode Read Data Generate Dummy Read Dummy Read Dummy Read from I2DR from I2DR STOP Signal from I2DR from I2DR And Store Figure 33-14. Flow-Chart of Typical I C Interrupt Routine 33-15 Freescale Semiconductor...
Page 842 C Interface Freescale Semiconductor 33-16...
Page 843 Freescale Semiconductor...
Page 844: Introduction
External development systems can access saved data, because the hardware supports concurrent operation of the processor and BDM-initiated commands. In addition, the option allows interrupts to occur. See Section 34.4.2, “Real-Time Debug Support”. Freescale Semiconductor 34-2...
Page 845 Finally, a serial BDM command is implemented ( ) to assist debugging when a software error FORCE generates an incorrect memory address that hangs the external bus. The BDM command attempts to break this condition by forcing a bus termination. 34-3 Freescale Semiconductor...
Page 846: Signal Descriptions
Halt status is reflected on processor status/debug data signals (PSTDDATA[7:0]) as multiple cycles of 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a debug interrupt exception in the processor. Freescale Semiconductor 34-4...
Page 847: Processor Status/Debug Data (Pstddata[7:0])
T+0, T+1 {PST for A, PST for B} T+2, T+3 {PST for C, PST for D} T+4, T+5 {PST for E, PST for F} The signal timing for the example in Table 34-3 is shown in Figure 34-2. 34-5 Freescale Semiconductor...
Page 848: Memory Map/Register Definition
WDEBUG instruction (write only). Therefore, the breakpoint hardware in debug module can be read or written by the external development system using the debug serial interface or written by the operating Freescale Semiconductor 34-6...
Page 849 Address low breakpoint register 1 (ABLR1) Undefined 34.3.8/34-19 0x1E Data breakpoint register 1 (DBR1) Undefined 34.3.9/34-20 0x1F Data breakpoint mask register 1 (DBMR1) Undefined 34.3.9/34-20 Each debug register is accessed as a 32-bit register; reserved fields are not used (don’t care). 34-7 Freescale Semiconductor...
Page 850: Shared Debug Resources
Revision B added hardware registers to eliminate these shared functions. The BAAR is used to specify bus attributes for BDM memory commands and has the same format as the LSB of the AATR. The registers containing the BDM memory address and the BDM data are not program visible. Freescale Semiconductor 34-8...
Page 851: Configuration/Status Register (Csr)
Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM. Reset or the debug HALT command clear HALT. Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM. Reset or the debug BKPT command clear BKPT. 34-9 Freescale Semiconductor...
Page 852 10 Capture all read data. 11 Capture all read and write data. User halt enable. Selects the CPU privilege level required to execute the HALT instruction. 0 HALT is a supervisor-only instruction. 1 HALT is a supervisor/user instruction. Freescale Semiconductor 34-10...
Page 853: Bdm Address Attribute Register (Baar)
1 Debug mode output is not asserted when the core is halted. 34.3.3 BDM Address Attribute Register (BAAR) The BAAR register defines the address space for memory-referencing BDM commands. BAAR[R, SZ] are loaded directly from the BDM command, while the low-order 5 bits can be programmed from the 34-11 Freescale Semiconductor...
Page 854: Address Attribute Trigger Registers (Aatr, Aatr1)
(XTDR) for AATR1. AATRn is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the command. WDMREG This register is expanded to include an optional ASID specification and a control bit that enables the use of the ASID field. Freescale Semiconductor 34-12...
Page 855 Transfer Modifier Mask. Setting a TMM bit masks the corresponding TM bit in address comparisons. Read/Write. R is compared with the R/W signal of the processor’s local bus. 6–5 Size. Compared to the processor’s local bus size signals. 00 Longword 01 Byte 10 Word 11 Reserved 34-13 Freescale Semiconductor...
Page 856: Trigger Definition Register (Tdr)
Disable TDR and XTDR (by clearing TDR[29,13] and XTDR[29,13]) before defining triggers. When performing a level-1, level-2, and level-1 breakpoint sequence, TDR[29] must be cleared in the level-2 breakpoint handler for the second level-1 breakpoint to occur. Freescale Semiconductor 34-14...
Page 857 Lower lower data byte. Low-order byte of the low-order word. Lower middle data byte. High-order byte of the low-order word. Upper middle data byte. Low-order byte of the high-order word. Upper upper data byte. High-order byte of the high-order word. 34-15 Freescale Semiconductor...
Page 858 Lower lower data byte. Low-order byte of the low-order word. Lower middle data byte. High-order byte of the low-order word. Upper middle data byte. Low-order byte of the high-order word. Upper upper data byte. High-order byte of the high-order word. Freescale Semiconductor 34-16...
Page 859: Program Counter Breakpoint/Mask Registers (Pbr0–3, Pbmr)
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 34-7. PC Breakpoint Register (PBR0) 34-17 Freescale Semiconductor...
Page 860: Pc Breakpoint Asid Control Register (Pbac)
PC Breakpoint ASID Control Register (PBAC) The PBAC register configures the breakpoint qualification for each PC breakpoint register (PBRn). Four bits are dedicated for each breakpoint register and specify how the ASID is used in PC breakpoint qualification. Freescale Semiconductor 34-18...
Page 861: Address Breakpoint Registers (Ablr/Ablr1, Abhr/Abhr1)
The trigger definition register (TDR) identifies the trigger as one of three cases: • Identically the value in ABLR • Inside the range bound by ABLR and ABHR inclusive • Outside that same range XTDR determines the same for ABLR1 and ABHR1. 34-19 Freescale Semiconductor...
Page 862: Data Breakpoint And Mask Registers (Dbr/Dbr1, Dbmr/Dbmr1)
Figure 34-12. Data Breakpoint Registers (DBR, DBR1) Table 34-17. DBR, DBR1 Field Descriptions Field Description 31–0 Data Breakpoint Value. Contains the value to be compared with the data value from the processor’s local bus as a Data breakpoint trigger. Freescale Semiconductor 34-20...
Page 863: Pc Breakpoint Asid Register (Pbasid)
PBASID and its exact inclusion within the breakpoint specification defined by the PBAC. PBASID contains one 8-bit ASID values for each PC breakpoint register, as described in Table 34-20, which allows each PC breakpoint register to be associated with a unique virtual address and process. 34-21 Freescale Semiconductor...
Page 864: Extended Trigger Definition Register (Xtdr)
A write to XTDR clears the CSR trigger status bits, CSR[BSTAT]. XTDR is accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the command. WDMREG Section 34.3.11.1, “Resulting Set of Possible Trigger Combinations,” describes how to handle multiple breakpoint conditions. Freescale Semiconductor 34-22...
Page 865 Level 2 data breakpoint invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a L2DI trigger based on the occurrence of a data value other than the DBR contents. 0 No inversion 1 Invert data breakpoint comparators. 34-23 Freescale Semiconductor...
Page 866 Level 1 data breakpoint invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a L1DI trigger based on the occurrence of a data value other than the DBR contents. 0 No inversion 1 Invert data breakpoint comparators. Freescale Semiconductor 34-24...
Page 867: Resulting Set Of Possible Trigger Combinations
Two-level triggers of the form: (PC_breakpoint) then if (Address_breakpoint{&& Data_breakpoint}) (PC_breakpoint) then if (Address_breakpoint{&& Data_breakpoint} Address1_breakpoint{&& Data1_breakpoint}) (PC_breakpoint) then if (Address1_breakpoint{&& Data1_breakpoint}) (Address_breakpoint {&& Data_breakpoint}) then if (Address1_breakpoint{&& Data1_breakpoint}) (Address1_breakpoint {&& Data1_breakpoint}) then if (Address_breakpoint{&& Data_breakpoint}) (Address_breakpoint {&& Data_breakpoint}) 34-25 Freescale Semiconductor...
Page 868: Functional Description
Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of priority: 1. A catastrophic fault-on-fault condition automatically halts the processor. Freescale Semiconductor 34-26...
Page 869 (0x8, 0x9, 0xA, or 0xB), PSTDDATA can display no more than four data 0xFFs. Two such scenarios exist: • A B marker occurs on the left nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xBF 0xFF 34-27 Freescale Semiconductor...
Page 870 DSI, on the rising edge of PSTCLK. DSO is delayed from the DSCLK-enabled PSTCLK rising edge (registered after a BDM state machine state change). All events in the debug module’s serial state machine are based on the PSTCLK rising edge. DSCLK must also be sampled low (on a positive edge of PSTCLK) Freescale Semiconductor 34-28...
Page 871: Receive Packet Format
Data. Contains the message to be sent from the debug module to the development system. The response message Data is always a single word, with the data field encoded as shown above. 34.4.1.3.1 Transmit Packet Format The basic transmit packet consists of 16 data bits and 1 reserved bit. 34-29 Freescale Semiconductor...
Page 872 8 bits of the response data undefined. Referenced data is returned in the lower 8 bits of the response. Operand Size Bit Values Byte 8 bits Word 16 bits Longword 32 bits Reserved — 5–4 Reserved, must be cleared. Freescale Semiconductor 34-30...
Page 873: Command Sequence Diagrams
Sequence taken if illegal command is received by debug module Sequence taken if bus error Results from previous command occurs on memory access Responses from the debug module High- and low-order 16 bits of result Figure 34-20. Command Sequence Diagram 34-31 Freescale Semiconductor...
Page 874 BDM command set. Subsequent sections contain detailed descriptions of each command. Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior. See Table 34-26 for register address encodings. Freescale Semiconductor 34-32...
Page 875 - Steal: Command generates bus cycles that can be interleaved with bus accesses. - Parallel: Command is executed in parallel with CPU activity. 0x4 is a three-bit field. Freescale reserves unassigned command opcodes. All unused command formats within any revision level perform a and return the illegal command response. 34-33 Freescale Semiconductor...
Page 876 The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: Register D[31:16] D[15:0] Figure 34-23. Command Format WAREG WDREG Freescale Semiconductor 34-34...
Page 877 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. Command/Result Formats: Byte Command A[31:16] A[15:0] Result D[7:0] Word Command A[31:16] A[15:0] Result D[15:0] Longword Command A[31:16] A[15:0] Result D[31:16] D[15:0] Figure 34-25. Command/Result Formats READ 34-35 Freescale Semiconductor...
Page 878 Write data to the memory location specified by the longword address. BAAR[TT,TM] defines address space. Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. Freescale Semiconductor 34-36...
Page 879 Debug Module Command Formats: Byte A[31:16] A[15:0] D[7:0] Word A[31:16] A[15:0] D[15:0] Longword A[31:16] A[15:0] D[31:16] D[15:0] Figure 34-27. Command Format WRITE 34-37 Freescale Semiconductor...
Page 880 The initial address increments by the operand size (1, 2, or 4) and saves in a temporary register. Subsequent commands use this address, perform the memory read, increment it by the current DUMP operand size, and store the updated address in the temporary register. Freescale Semiconductor 34-38...
Page 881 ’NOT READY’ BERR ’NOT READY’ READ DUMP (LONG) MEMORY ’NOT READY’ LOCATION NEXT CMD NEXT CMD MS RESULT LS RESULT NEXT CMD NEXT CMD ’ILLEGAL’ ’NOT READY’ BERR ’NOT READY’ Figure 34-30. Command Sequence DUMP Operand Data: None 34-39 Freescale Semiconductor...
Page 882 The size field is examined each time a command is processed, allowing the operand size to be altered FILL dynamically. Command Formats: Byte D[7:0] Word D[15:0] Longword D[31:16] D[15:0] Figure 34-31. Command Format FILL Freescale Semiconductor 34-40...
Page 883 BDM command while the processor is halted, the updated value is used when prefetching resumes. If a command issues and the CPU is not halted, the command is ignored. Figure 34-33. Command Format Command Sequence: NEXT CMD ’CMD COMPLETE’ Figure 34-34. Command Sequence 34-41 Freescale Semiconductor...
Page 884 If the option to display ASID is enabled (CSR[OTE] = 1), the 8-bit ASID follows the address. That is, the PSTDDATA sequence is {0x5, Marker, Instruction Address, 0x8, ASID}, where the 0x8 is the marker for the ASID. Freescale Semiconductor 34-42...
Page 885 — It is assumed the processor is already halted at the time of the errant BDM access. To resolve the hung bus, it is necessary to process four or more commands, because the BDM FORCE command may have initiated a cache line access that fetches 4 longwords, each needing a unique transfer acknowledge. 34-43 Freescale Semiconductor...
Page 886 32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. The 12-bit Rc field is the same the processor’s MOVEC instruction uses. Command/Result Formats: Command Result D[31:16] D[15:0] Figure 34-41. Command/Result Formats RCREG Freescale Semiconductor 34-44...
Page 887 MAC Status Register (MACSR) 0x805 MAC Mask Register (MASK) 0x806 MAC Accumulator 0 (ACC0) 0x807 MAC Accumulator 0,1 Extension Bytes (ACCEXT01) 0x808 MAC Accumulator 2,3 Extension Bytes (ACCEXT23) 0x809 MAC Accumulator 1 (ACC1) 0x80A MAC Accumulator 2 (ACC2) 34-45 Freescale Semiconductor...
Page 888 Likewise, to write an accumulator register, the following BDM sequence is needed: BdmWriteACCx ( rcreg macsr; // read current macsr contents and save wcreg #0,macsr; // disable all rounding modes wcreg #data,ACCx; // write the desired accumulator wcreg #saved_data,macsr;// restore the original macsr Freescale Semiconductor 34-46...
Page 889 Result Data: Successful write operations return 0xFFFF. Bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of 0x0001. 34-47 Freescale Semiconductor...
Page 890 The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction. Freescale Semiconductor 34-48...
Page 891: Real-Time Debug Support
(CSR[BSTAT]) is provided on the PSTDDATA output port of the DDATA information when it is not displaying captured processor status, operands, or branch addresses. Section 34.4.4.2, “Processor Stopped or Breakpoint State Change (PST = 0xE).” 34-49 Freescale Semiconductor...
Page 892 PC breakpoints from other trigger events. Table 34-29. Exception Vector Assignments Vector Number Vector Offset (Hex) Stacked Program Counter Assignment 0x030 Next Non-PC-breakpoint debug interrupt 0x034 Next PC-breakpoint debug interrupt Freescale Semiconductor 34-50...
Page 893 Thus, all hardware breakpoints are disabled until the first instruction after the RTE completes execution, regardless of the programmed trigger response. 34.4.2.2 Emulator Mode Emulator mode facilitates non-intrusive emulator functionality. This mode can be entered in three different ways: 34-51 Freescale Semiconductor...
Page 894: Concurrent Bdm And Processor Operation
(DSCLK must be inactive). 34.4.4 Real-Time Trace Support Real-time trace, which defines the dynamic execution path and is also known as instruction trace, is a fundamental debug function. The ColdFire solution is to include a parallel output port providing encoded Freescale Semiconductor 34-52...
Page 895 PSTDDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is signaled, followed by the appropriate marker, and then the data transfer on the PSTDDATA port. Transfer length depends on the WDDATA operand size. 34-53 Freescale Semiconductor...
Page 896 For such change-of-flow operations, the ColdFire processor uses the debug pins to output the following sequence of information on two successive processor clock cycles: 1. Use PSTDDATA (0x5) to identify that a taken branch is executed. Freescale Semiconductor 34-54...
Page 897 — 0x2 = waiting for level-1 breakpoint — 0x4 = level-1 breakpoint triggered — 0xA = waiting for level-2 breakpoint — 0xC = level-2 breakpoint triggered Thus, 0xE can indicate multiple events, based on the next value, as Table 34-31 shows. 34-55 Freescale Semiconductor...
Page 898 The B marker occurs on the least-significant nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xYB 0xFF 0xFF 0xFF 0xFF 0xXY (X indicates the PST value is guaranteed not to be 0xF, and Y signifies a PSTDDATA value that doesn’t affect the 0xFF count.) Freescale Semiconductor 34-56...
Page 899: User Instruction Set
PSTDDATA = 0x1, {0xB, source operand} and.l Dy,<ea>x PSTDDATA = 0x1, {0xB, source}, {0xB, destination} andi.l #<data>,Dx PSTDDATA = 0x1 asl.l {Dy,#<data>},Dx PSTDDATA = 0x1 asr.l {Dy,#<data>},Dx PSTDDATA = 0x1 bcc.{b,w} if taken, then PSTDDATA = 0x5, else PSTDDATA = 0x1 34-57 Freescale Semiconductor...
Page 900 <ea>y,Dx PSTDDATA = 0x1, {0x9, source operand} eor.l Dy,<ea>x PSTDDATA = 0x1, {0xB, source}, {0xB, destination} eori.l #<data>,Dx PSTDDATA = 0x1 ext.l PSTDDATA = 0x1 ext.w PSTDDATA = 0x1 extb.l PSTDDATA = 0x1 illegal PSTDDATA = 0x1 Freescale Semiconductor 34-58...
Page 901 PSTDDATA = 0x1 not.l PSTDDATA = 0x1 or.l <ea>y,Dx PSTDDATA = 0x1, {0xB, source operand} or.l Dy,<ea>x PSTDDATA = 0x1, {0xB, source}, {0xB, destination} ori.l #<data>,Dx PSTDDATA = 0x1 pea.l <ea>y PSTDDATA = 0x1, {0xB, destination operand} 34-59 Freescale Semiconductor...
Page 902 PSTDDATA = 0x1, {0x9, source operand} unlk PSTDDATA = 0x1, {0xB, destination operand} wddata.b <ea>y PSTDDATA = 0x4, {0x8, source operand} wddata.l <ea>y PSTDDATA = 0x4, {0xB, source operand} wddata.w <ea>y PSTDDATA = 0x4, {0x9, source operand} Freescale Semiconductor 34-60...
Page 903 PSTDDATA = 0x1 move.l {Ry,#<data>},ACCext23 PSTDDATA = 0x1 move.l ACCext01,Rx PSTDDATA = 0x1 move.l ACCext23,Rx PSTDDATA = 0x1 move.l ACCy,ACCx PSTDDATA = 0x1 move.l ACCy,Rx PSTDDATA = 0x1 move.l MACSR,CCR PSTDDATA = 0x1 move.l MACSR,Rx PSTDDATA = 0x1 34-61 Freescale Semiconductor...
Page 904: Supervisor Instruction Set
0xD is signaled. Similar to the exception processing mode, the stopped state (PSTDDATA nibble = 0xE) and the halted state (PSTDDATA = 0xFF) display this status throughout the entire time the ColdFire processor is in the given mode. Freescale Semiconductor 34-62...
Page 905: Freescale-Recommended Bdm Pinout
The ColdFire BDM connector is a 26-pin Berg connector arranged 2 x 13 as shown below. Developer reserved BKPT DSCLK Developer reserved RESET EVDD PSTDDATA7 PSTDDATA6 PSTDDATA5 PSTDDATA4 PSTDDATA3 PSTDDATA1 PSTDDATA2 PSTDDATA0 Freescale reserved Freescale reserved PSTCLK IVDD Pins reserved for BDM developer use. Supplied by target Figure 34-50. Recommended BDM Connector 34-63 Freescale Semiconductor...
Page 906: Introduction
32-bit IDCODE Register TDO/DSO 1-bit TEST_CTRL Register 5-bit TAP Instruction Decoder 5-bit TAP Instruction Register JTAG_EN TCLK Disable DSCLK TMS/BKPT Force BKPT = 1 TRST/DSCLK JTAG Module to Debug Module BKPT DSCLK Figure 35-1. JTAG Block Diagram Freescale Semiconductor 35-1...
Page 907: Features
The JTAG_EN pin selects between the debug module and JTAG. If JTAG_EN is low, the debug module is selected; if it is high, the JTAG is selected. Table 35-2 summarizes the pin function selected depending on JTAG_EN logic state. 35-2 Freescale Semiconductor...
Page 908: Test Clock Input (Tclk)
The TDI pin receives serial test and data, which is sampled on the rising edge of TCLK. Register values are shifted in least significant bit (lsb) first. The TDI pin has an internal pull-up resistor. The DSI pin provides data input for the debug module serial communication port. Freescale Semiconductor 35-3...
Page 909: Test Reset/Development Serial Clock (Trst/Dsclk)
TCLK. The msb of the IR is the bit closest to the TDI pin, and the lsb is the bit closest to the TDO pin. See Section 35.4.3, “JTAG Instructions” for a list of possible instruction codes. TAP state: Update-IR Access: User read/write Instruction Code Reset Figure 35-2. 5-Bit Instruction Register (IR) 35-4 Freescale Semiconductor...
Page 910: Idcode Register
0x04D MCF54451 0x04B MCF54452 0x049 MCF54453 0x04A MCF54454 0x048 MCF54455 11–1 Joint Electron Device Engineering Council ID bits. Indicate the reduced JEDEC ID for Freescale (0x0E). JEDEC IDCODE register ID. This bit is set to 1 to identify the register as the IDCODE register and not the bypass register according to the IEEE standard 1149.1.
Page 911: Boundary Scan Register
Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state. As Figure 35-5 shows, holding TMS at logic 1 while clocking TCLK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state. 35-6 Freescale Semiconductor...
Page 912: Jtag Instructions
Instruction Summary IDCODE 00001 Selects IDCODE register for shift SAMPLE/PRELOAD 00010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation SAMPLE 00011 Selects boundary scan register for shifting and sampling without disturbing functional operation Freescale Semiconductor 35-7...
Page 913: Idcode Instruction
IR contains the 0x2 opcode. The sampled data is accessible by shifting it through the boundary scan register to the TDO output by using the shift-DR state. The data capture and the shift operation are transparent to system operation. 35-8 Freescale Semiconductor...
Page 914 The shift register lsb is forced to logic 0 on the rising edge of TCLK after entry into the capture-DR state. Therefore, the first bit shifted out after selecting the bypass register is always logic 0. This differentiates parts that support an IDCODE register from parts that support only the bypass register. Freescale Semiconductor 35-9...
Page 915: Nonscan Chain Operation
It is recommended that TMS, TDI, TCLK, and TRST be pulled up. TRST could be connected to ground. However, because there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST. 35-10 Freescale Semiconductor...
Page 916: Appendix A Revision History
Controller is only one version of this register located in the INTC0 space. Edge Port Added bit 0 for each EPORT register, although this bit may not be used on this particular device. Added external signal timing section. Freescale Semiconductor...
Page 917 Added the following dTD Token[Total Bytes] field description: “For OUT transfers the total bytes must be evenly divisible by the maximum packet length.” Added note at beginning of chapter: “The MCF54450 and MCF54451 devices only contain a 24-bit PCI_AD bus, Controller PCI_AD[23:0].” Freescale Semiconductor...
Page 918 The serial configuration depends on the package of the device. Added serial configuration during reset for 256-pin devices table 256-pin devices use a different SBF reset configuration data. Added new SPI memory organization table for these devices. Edge Port Changed EPFR figure’s write row entries to w1c. Freescale Semiconductor...
Page 919 Corrected DSPIn_MCR bit 11 in field description table from CLR_TX to CLR_TXF. DSPI Added note to DSPI_MCR[CLR_TXF and CLR_RXF]. Added note to FIFO Disable Operation section. Removed “Support for 3.3-V tolerant devices” from features list as the device supports various other tolerances Freescale Semiconductor...
Page 920 UART Status Register bit 3 corrected from “TEMP" to “TXEMP" in field description table. SDRAMC Made changes to Layout Considerations section because MCF54455 has a true SSTL pad. Cache Changed the ACRn register diagram to show the SP bit as write-only.
Page 921 Revision History Freescale Semiconductor...

Freescale Semiconductor MCF54455 Reference Manual

Revision History

Chapter 1 Overview

Chapter 3 Coldfire Core

Chapter 4 Memory Management Unit (MMU)

Chapter 5 Enhanced Multiply-Accumulate Unit (EMAC)

Chapter 6 Cache

Chapter 7 Static RAM (SRAM)

Chapter 11

Chapter 8

Chapter 9

Chapter 10

Chapter 12

Chapter 15

Chapter 26

Chapter 17

Chapter 29

Chapter 18

Chapter 19

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Summary of Contents for Freescale Semiconductor MCF54455