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ABLR, ABLR1, ABHR and ABHR1 are accessible in supervisor mode using the WDEBUG instruction
and via the BDM port using the
DRc[4:0]: 0x0C (ABHR)
0x0D (ABLR)
0x1C (ABHR1)
0x1D (ABLR1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 34-11. Address Breakpoint Registers (ABLR, ABHR, ABLR1, ABHR1)
Field
31–0
Low Address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for
Address
specific single addresses are programmed into ABLR or ABLR1.
Field
31–0
High Address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
Address
34.3.9
Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1)
The data breakpoint registers (DBR/DBR1), specify data patterns used as part of the trigger into debug
mode. DBRn bits are masked by setting corresponding DBMR bits, as defined in TDR.
DBR, DBR1, DBMR, and DBMR1 are accessible in supervisor mode using the WDEBUG instruction and
through the BDM port using the
DRc[4:0]: 0x0E (DBR)
0x1E (DBR1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Field
31–0
Data Breakpoint Value. Contains the value to be compared with the data value from the processor's local bus as a
Data
breakpoint trigger.
Freescale Semiconductor
command.
WDMREG
Table 34-15. ABLR and ABLR1 Field Description
Table 34-16. ABHR and ABHR1 Field Description
command.
WDMREG
Figure 34-12. Data Breakpoint Registers (DBR, DBR1)
Table 34-17. DBR, DBR1 Field Descriptions
Access: Supervisor write-only
Address
Description
Description
Access: Supervisor write-only
Data
Description
Debug Module
BDM write-only
8
7
6
5
4
3
2
1
0
BDM write-only
8
7
6
5
4
3
2
1
0
34-20
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