Freescale Semiconductor MCF52277 Manuals

Manuals and User Guides for Freescale Semiconductor MCF52277. We have 1 Freescale Semiconductor MCF52277 manual available for free PDF download: Reference Manual

Freescale Semiconductor MCF52277 Reference Manual (801 pages)

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 10 MB

MCF52277 Reference Manual
22
About this Book
23
General Information
26
Acronyms and Abbreviations
28
Revision History
31
Mcf5227X Family Comparison
33
Block Diagram
35
Features
36
Phase Locked Loop (PLL)
37
Liquid Crystal Display Controller (LCDC)
38
SDR/DDR SDRAM Controller
39
Real Time Clock
40
Pulse Width Modulation (PWM) Module
41
DMA Controller
42
Internal Peripheral Space
43
Documentation
44
Introduction
45
Signal Primary Functions
50
PLL and Clock Signals
51
SDRAM Controller Signals
52
Serial Boot Facility Signals
53
LCD Controller Signals
54
Universal Serial Bus (USB) On-The-Go Signals
55
UART Module Signals
56
DMA Timer Signals
57
Test Signals
59
Introduction
61
Memory Map/Register Description
62
Data Registers (D0–D7)
64
Supervisor/User Stack Pointers (A7 and OTHER_A7)
65
Condition Code Register (CCR)
66
Program Counter (PC)
67
Status Register (SR)
68
Functional Description
69
Instruction Set Architecture (ISA_A+)
74
Exception Processing Overview
75
Exception Stack Frame Definition
77
Processor Exceptions
78
Address Error Exception
79
Debug Interrupt
81
Interrupt Exception
82
Reset Exception
82
Instruction Execution Timing
85
Move Instruction Execution Times
86
Miscellaneous Instruction Execution Times
90
Emac Instruction Execution Times
91
Introduction
93
Memory Map/Register Definition
95
Mask Register (MASK)
97
Accumulator Registers (ACC0–3)
98
Accumulator Extension Registers (Accext01, Accext23)
99
Functional Description
100
Fractional Operation Mode
102
EMAC Instruction Set Summary
104
EMAC Instruction Execution Times
105
Data Representation
106
Introduction
113
Memory Map/Register Definition
114
Cache Control Register (CACR)
115
Access Control Registers (ACR0, ACR1)
118
Functional Description
119
Memory Reference Attributes
120
Cache Miss Fetch Algorithm/Line Fills
121
Introduction
123
Memory Map/Register Description
124
Initialization/Application Information
126
Power Management
127
Introduction
129
Block Diagram
131
Modes of Operation
132
Memory Map/Register Definition
133
PLL Control Register (PCR)
134
PLL Status Register (PSR)
136
Lock Conditions
137
System Clock Modes
138
Clock Operation During Reset
139
Introduction
141
Wake-Up Control Register (WCR)
142
Peripheral Power Management Set Register (PPMSR)
143
Peripheral Power Management Clear Register (PPMCR)
144
Low-Power Control Register (LPCR)
147
Limp Mode
148
Peripheral Behavior in Low-Power Modes
149
Clock Module
151
Reset Controller
151
Lcd Controller
154
Introduction
157
External Signal Descriptions
158
Chip Configuration Register (CCR)
159
Reset Configuration Register (RCON)
160
Chip Identification Register (CIR)
161
Clock-Divider Register (CDR)
164
Functional Description
165
Boot Configuration
170
Low Power Configuration
171
Introduction
173
Features
174
Serial Boot Facility Control Register (SBFCR)
175
Functional Description
176
Reset Configuration and Optional Boot Load
177
Initialization Information
178
FAST_READ Feature Initialization
179
Introduction
181
External Signal Description
182
Reset Control Register (RCR)
183
Functional Description
184
Reset Control Flow
185
Concurrent Resets
187
Introduction
189
Memory Map/Register Definition
190
Peripheral Access Control Registers (Pacrx)
191
Core Watchdog Control Register (CWCR)
195
Core Watchdog Service Register (CWSR)
196
Burst Configuration Register (BCR)
197
Core Fault Address Register (CFADR)
198
Core Fault Location Register (CFLOC)
199
Core Fault Data Register (CFDTR)
200
Functional Description
201
Core Data Fault Recovery Registers
202
Overview
203
Features
204
Modes of Operation
205
XBS Control Registers (Xbs_Crsn)
207
Functional Description
208
Initialization/Application Information
209
Introduction
211
Overview
212
External Signal Description
213
Memory Map/Register Definition
219
Port Output Data Registers (Podr_X)
221
Port Data Direction Registers (Pddr_X)
222
Port Pin Data/Set Data Registers (Ppdsdr_X)
223
Port Clear Output Data Registers (Pclrr_X)
225
Pin Assignment Registers (Par_X)
226
Flexbus Mode Select Control Register (MSCR_FLEXBUS)
233
SDRAM Mode Select Control Register (MSCR_SDRAM)
234
Drive Strength Control Registers (Dscr_X)
235
Functional Description
236
Port Digital I/O Timing
237
Initialization/Application Information
238
Introduction
239
Memory Map/Register Definition
240
Interrupt Pending Registers (Iprhn, Iprln)
242
Interrupt Mask Register (Imrhn, Imrln)
243
Interrupt Force Registers (Intfrchn, Intfrcln)
244
Interrupt Configuration Register (Iconfign)
245
Set Interrupt Mask Register (Simrn)
246
Current Level Mask Register (CLMASK)
247
Saved Level Mask Register (SLMASK)
248
Interrupt Control Register (Icr0N, Icr1N, (N = 00, 01, 02, ..., 63))
249
Interrupt Sources
250
Software and Level 1–7 IACK Registers (Swiackn, L1Iackn–L7Iackn)
252
Functional Description
254
Prioritization between Interrupt Controllers
255
Low-Power Wake-Up Operation
256
Introduction
259
Low-Power Mode Operation
260
EPORT Pin Assignment Register (EPPAR)
261
EPORT Data Direction Register (EPDDR)
262
Edge Port Interrupt Enable Register (EPIER)
263
Edge Port Pin Data Register (EPPDR)
264
Overview
265
Features
266
Debug Mode
267
Memory Map/Register Definition
268
Edma Error Status Register (EDMA_ES)
269
Edma Enable Request Register (EDMA_ERQ)
272
Edma Enable Error Interrupt Registers (EDMA_EEI)
273
Edma Set Enable Request Register (EDMA_SERQ)
274
Edma Set Enable Error Interrupt Register (EDMA_SEEI)
275
Edma Clear Interrupt Request Register (EDMA_CINT)
276
Edma Clear Error Register (EDMA_CERR)
277
Edma Clear DONE Status Bit Register (EDMA_CDNE)
278
Edma Interrupt Request Register (EDMA_INT)
279
Edma Channel N Priority Registers (Dchprin)
280
Transfer Control Descriptors (Tcdn)
281
Functional Description
288
Edma Basic Data Flow
289
Initialization/Application Information
292
DMA Programming Errors
295
DMA Transfer
296
Edma Tcdn Status Monitoring
299
Channel Linking
300
Dynamic Programming
301
Introduction
303
Features
304
Byte Enables/Byte Write Enables (FB_BE/BWE[3:0])
305
Memory Map/Register Definition
306
Chip-Select Mask Registers (CSMR0–CSMR5)
307
Chip-Select Control Registers (CSCR0–CSCR5)
308
Functional Description
311
Data Transfer Operation
312
Data Byte Alignment and Physical Connections
313
Flexbus Timing Examples
314
Basic Read Bus Cycle
315
Basic Write Bus Cycle
316
Timing Variations
320
Burst Cycles
325
Misaligned Operands
329
Bus Errors
330
Introduction
331
Block Diagram
332
Terminology
333
Interface Recommendations
335
SDRAM SDR Connections
340
SDRAM DDR Component Connections
342
Termination Example
343
Memory Map/Register Definition
344
SDRAM Control Register (SDCR)
345
SDRAM Configuration Register 1 (SDCFG1)
347
SDRAM Configuration Register 2 (SDCFG2)
349
SDRAM Chip Select Configuration Registers (Sdcsn)
350
Functional Description
351
Initialization/Application Information
356
Page Management
357
Transfer Size
358
Introduction
359
Block Diagram
360
Modes of Operation
361
External Signal Description
362
Memory Map/Register Definition
364
Module Identification Registers
366
Device/Host Timer Registers
369
Capability Registers
370
Operational Registers
374
Functional Description
403
Initialization/Application Information
404
Device Data Structures
405
Device Operation
412
Servicing Interrupts
430
Deviations from the EHCI Specifications
431
Introduction
437
External Signal Description
439
LCDC Screen Start Address Register (LCD_SSAR)
440
LCDC Size Register (LCD_SR)
441
LCDC Cursor Position Register (LCD_CPR)
442
LCDC Cursor Width Height and Blink Register (LCD_CWHB)
443
LCDC Color Cursor Mapping Register (LCD_CCMR)
444
LCDC Panel Configuration Register (LCD_PCR)
445
LCDC Horizontal Configuration Register (LCD_HCR)
448
LCDC Panning Offset Register (LCD_POR)
449
LCDC Sharp Configuration Register (LCD_SCR)
450
LCDC PWM Contrast Control Register (LCD_PCCR)
452
LCDC Refresh Mode Control Register (LCD_RMCR)
453
LCDC Interrupt Configuration Register (LCD_ICR)
454
LCDC Interrupt Enable Register (LCD_IER)
455
LCDC Interrupt Status Register (LCD_ISR)
456
LCDC Graphic Window Start Address Register (LCD_GWSAR)
458
LCDC Graphic Window Virtual Page Width Register (LCD_GWVPW)
459
LCDC Graphic Window Position Register (LCD_GWPR)
460
LCDC Graphic Window DMA Control Register (LCD_GWDCR)
462
Functional Description
465
Graphic Window on Screen
466
Panning
467
Black-And-White Operation
469
Color Generation
470
Frame Rate Modulation Control (FRC)
472
Panel Interface Signals and Timing
473
Bpp Mode Color STN Panel
476
Overview
481
Features
482
External Signal Description
483
ASP Control Register (ASP_CR)
484
ASP Sample Setting Register (ASP_SET)
487
ASP Sample Timing Register (ASP_TIM)
488
ASP Interrupt/Dma Control Register (ASP_ICR)
489
ASP Status Register (ASP_SR)
490
ASP Sample FIFO (ASP_SFIFO)
491
ASP FIFO Pointer Register (ASP_FIFOP)
492
ASP Clock Divider Register (ASP_CLKD)
493
Touchscreen Controller Function
494
General ADC Function
496
Initialization/Application Information
497
Touchscreen Mode 01—Single Round
499
Touchscreen Mode 01—Auto
500
Touchscreen Mode 10—Single Round
501
Touchscreen Mode 10—Auto
502
Touchscreen Mode 11—Single Round
503
Touchscreen Mode 11—Auto
504
General Purpose Adc—Single Round
506
Touchscreen Calibration—Single Round
507
Touchscreen Calibration – Auto
508
Introduction
511
The Can System
512
Features
513
Modes of Operation
514
External Signal Description
515
Flexcan Configuration Register (CANMCR)
516
Flexcan Control Register (CANCTRL)
519
Flexcan Free Running Timer Register (TIMER)
521
Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK)
522
Flexcan Error Counter Register (ERRCNT)
523
Flexcan Error and Status Register (ERRSTAT)
524
Interrupt Mask Register (IMASK)
526
Interrupt Flag Register (IFLAG)
527
Rx Individual Masking Registers (RXIMR0–15)
531
Functional Overview
532
Arbitration Process
533
Matching Process
534
Message Buffer Managing
535
Locking and Releasing Message Buffers
536
CAN Protocol Related Frames
537
Time Stamp
538
Initialization/Application Information
540
Interrupts
541
Introduction
543
Memory Map/Register Definition
544
PWM Enable Register (PWME)
545
PWM Polarity Register (PWMPOL)
546
PWM Prescale Clock Select Register (PWMPRCLK)
547
PWM Center Align Enable Register (PWMCAE)
548
PWM Scale a Register (PWMSCLA)
549
PWM Scale B Register (PWMSCLB)
550
PWM Channel Counter Registers (Pwmcntn)
551
PWM Channel Period Registers (Pwmpern)
552
PWM Shutdown Register (PWMSDN)
553
Functional Description
554
PWM Channel Timers
556
Introduction
569
Overview
570
Features
571
External Signal Description
573
Memory Map/Register Definition
575
SSI Transmit Data Registers 0 & 1 (SSI_TX0/1)
576
SSI Receive Data Registers 0 & 1 (SSI_RX0/1)
578
SSI Receive FIFO 0 & 1 Registers
579
SSI Control Register (SSI_CR)
580
SSI Interrupt Status Register (SSI_ISR)
582
SSI Interrupt Enable Register (SSI_IER)
588
SSI Transmit Configuration Register (SSI_TCR)
589
SSI Receive Configuration Register (SSI_RCR)
591
SSI Clock Control Register (SSI_CCR)
592
SSI FIFO Control/Status Register (SSI_FCSR)
593
SSI AC97 Control Register (SSI_ACR)
595
SSI AC97 Command Address Register (SSI_ACADD)
596
SSI AC97 Command Data Register (SSI_ACDAT)
597
SSI Receive Time Slot Mask Register (SSI_RMASK)
598
Normal Mode
599
Ac97 Mode
609
SSI Clocking
611
External Frame and Clock Operation
614
Receive Interrupt Enable Bit Description
616
Initialization/Application Information
617
Introduction
619
Features
620
External Signal Description
621
RTC Seconds Counter Register (RTC_SECONDS)
622
RTC Seconds Alarm Register (RTC_ALRM_SEC)
623
RTC Interrupt Status Register (RTC_ISR)
624
RTC Interrupt Enable Register (RTC_IER)
625
RTC Stopwatch Minutes Register (RTC_STPWCH)
627
RTC General Oscillator Clock Upper Register (RTC_GOCU)
628
Functional Description
629
Alarm
630
Minute Stopwatch
631
Introduction
633
Memory Map/Register Definition
634
PIT Control and Status Register (Pcsrn)
635
PIT Modulus Register (Pmrn)
636
PIT Count Register (Pcntrn)
637
Free-Running Timer Operation
638
Introduction
641
Features
642
DMA Timer Mode Registers (Dtmrn)
643
DMA Timer Extended Mode Registers (Dtxmrn)
644
DMA Timer Event Registers (Dtern)
645
DMA Timer Reference Registers (Dtrrn)
646
DMA Timer Capture Registers (Dtcrn)
647
Functional Description
648
Initialization/Application Information
649
Calculating Time-Out Values
650
Introduction
651
Features
652
Modes of Operation
653
External Signal Description
654
Serial Clock (DSPI_SCK)
655
DSPI Transfer Count Register (DSPI_TCR)
658
DSPI Status Register (DSPI_SR)
663
DSPI Dma/Interrupt Request Select and Enable Register (DSPI_RSER)
665
DSPI PUSH TX FIFO Register (DSPI_PUSHR)
666
DSPI POP RX FIFO Register (DSPI_POPR)
668
DSPI Receive FIFO Registers 0–15 (Dspi_Rxfrn)
669
Functional Description
670
Serial Peripheral Interface (SPI) Configuration
671
Master Mode
672
Slave Mode
672
Fifo Disable Operation
672
Tx Fifo Buffering Mechanism
672
Rx Fifo Buffering Mechanism
673
DSPI Baud Rate and Clock Delay Generation
674
Transfer Formats
676
Continuous Selection Format
680
Continuous Serial Communications Clock
682
Interrupts/Dma Requests
683
Power Saving Features
685
Initialization/Application Information
686
Delay Settings
687
Calculation of FIFO Pointer Addresses
688
Introduction
691
Features
692
External Signal Description
693
UART Mode Registers 1 (Umr1N)
695
UART Mode Register 2 (Umr2N)
696
UART Status Registers (Usrn)
697
UART Clock Select Registers (Ucsrn)
699
UART Receive Buffers (Urbn)
701
UART Transmit Buffers (Utbn)
702
UART Auxiliary Control Register (Uacrn)
703
UART Baud Rate Generator Registers (Ubg1N/Ubg2N)
705
UART Output Port Command Registers (Uop1N/Uop0N)
706
Transmitter and Receiver Operating Modes
708
Looping Modes
712
Automatic Echo Mode
713
Local Loopback Mode
713
Remote Loopback Mode
713
Multidrop Mode
714
Bus Operation
716
UART Module Initialization Sequence
718
Introduction
725
Overview
726
Memory Map/Register Definition
727
Functional Description
731
Slave Address Transmission
732
Acknowledge
733
Clock Synchronization and Arbitration
735
Handshaking and Clock Stretching
736
Post-Transfer Software Response
737
Generation of Repeated START
738
Introduction
741
Signal Descriptions
742
Real-Time Trace Support
743
Begin Execution of Taken Branch (PST = 0X5)
744
Memory Map/Register Definition
745
Shared Debug Resources
747
BDM Address Attribute Register (BAAR)
750
Address Attribute Trigger Register (AATR)
751
Trigger Definition Register (TDR)
752
Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR)
755
Address Breakpoint Registers (ABLR, ABHR)
757
Data Breakpoint and Mask Registers (DBR, DBMR)
758
Background Debug Mode (BDM)
759
BDM Serial Interface
760
Receive Packet Format
761
BDM Command Set
762
Coldfire Bdm Command Format
764
Command Sequence Diagrams
765
Command Set Descriptions
766
Real-Time Debug Support
780
Concurrent BDM and Processor Operation
782
Processor Status, Debug Data Definition
783
Supervisor Instruction Set
788
Freescale-Recommended BDM Pinout
789
Introduction
791
Features
792
Test Clock Input (TCLK)
793
Test Reset/Development Serial Clock (TRST/DSCLK)
794
IDCODE Register
795
Boundary Scan Register
796
JTAG Instructions
797
Idcode Instruction
798
Highz Instruction
799
Clamp Instruction
799
Bypass Instruction
799
Initialization/Application Information
800

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Freescale Semiconductor MCF52277 Reference Manual (801 pages)

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