Serial Input (Dspi_Sin) - Freescale Semiconductor MCF54455 Reference Manual

In master mode and when the DSPI_MCR[PCSSE] bit is set, DSPI_PCSS provides a strobe signal that can
be used with an external logic device for deglitching of the PCS signals. DSPI_PCSS provides the
appropriate timing for the decoding of the DSPI_PCS[0:3] signals which prevents glitches from occurring.
DSPI_PCS5/PCSS is not used in slave mode.
31.2.5

Serial Input (DSPI_SIN)

DSPI_SIN is a serial data input signal.
31.2.6 Serial Output (DSPI_SOUT)
DSPI_SOUT is a serial data output signal.
31.2.7 Serial Clock (DSPI_SCK)
DSPI_SCK is a serial communication clock signal. In master mode, DSPI generates DSPI_SCK. In slave
mode, DSPI_SCK is an input from an external bus master.
31.3 Memory Map/Register Definition
Table 31-2 shows the DSPI memory map.
Address
0xFC05_C000 DSPI module configuration register (DSPI_MCR)
0xFC05_C008 DSPI transfer count register (DSPI_TCR)
0xFC05_C00C DSPI clock and transfer attributes registers (DSPI_CTARn),
+ (n 0x04)
n=0:7
0xFC05_C02C DSPI status register (DSPI_SR)
0xFC05_C030 DSPI DMA/interrupt request select and enable register
(DSPI_RSER)
0xFC05_C034 DSPI push TX FIFO register (DSPI_PUSHR)
0xFC05_C038 DSPI pop RX FIFO register (DSPI_POPR)
0xFC05_C03C DSPI transmit FIFO registers (DSPI_TXFRn),
+ (n 0x04)
n=0:15
0xFC05_C07C DSPI receive FIFO registers (DSPI_RXFRn),
+ (n 0x04)
n=0:15
31.3.1 DSPI Module Configuration Register (DSPI_MCR)
The DSPI_MCR contains bits that configure various attributes associated with DSPI operation. The HALT
and MDIS bits can be changed at any time, but only take effect on the next frame boundary. Only the HALT
and MDIS bits in the DSPI_MCR may be changed while the DSPI is running.
Freescale Semiconductor
Table 31-2. DSPI Module Memory Map
Register
DMA Serial Peripheral Interface (DSPI)
Width Access Reset Value
32 R/W 0x0000_4001
32 R/W 0x0000_0000
32 R/W 0x7800_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R 0x0000_0000
32 R 0x0000_0000
32 R 0x0000_0000
Section/Page
31.3.1/31-5
31.3.2/31-8
31.3.3/31-8
31.3.4/31-14
31.3.5/31-16
31.3.6/31-17
31.3.7/31-19
31.3.8/31-19
31.3.9/31-20
31-5