Ssi Receive Data Registers 0 And 1 (Ssi_Rx0/1) - Freescale Semiconductor MCF54455 Reference Manual

Synchronous Serial Interface (SSI)
31
16 bits
20 bits
24 bits
31
TXSR
Figure 27-6. Transmit Data Path (TXBIT0=0, TSHFD=1) (msb Alignment)
31
SSI_TXD
Figure 27-7. Transmit Data Path (TXBIT0=1, TSHFD=0) (lsb Alignment)
31
24 bits
TXSR
Figure 27-8. Transmit Data Path (TXBIT0=1, TSHFD=1) (lsb Alignment)
27.3.4

SSI Receive Data Registers 0 and 1 (SSI_RX0/1)

The SSI_RX0/1 registers store the data received by the SSI. For details on data alignment see
Section 27.3.6, "SSI Receive Shift Register (RXSR)."
27-10
15
12 bits
15
16 bits
23 19
16 bits
20 bits
24 bits
23 19
23 19 15
12 bits
16 bits
20 bits
23 19 15
11 7
11 7
20 bits 24 bits 12 bits
15 11
12 bits
15 11
11
11
0
SSI_TX
0
SSI_TXD
0
SSI_TX
0
TXSR
0
SSI_TX
0
SSI_TXD
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