Freescale Semiconductor MCF54455 Reference Manual page 251

Universal Serial Bus Interface – On-The-Go Module
Field
15–4 Reserved, must be cleared
3–0 Endpoint receive complete event. Each bit indicates a received event (OUT/SETUP) occurs and software must
ERCE read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the
transfer descriptor, this bit is set simultaneously with the USBINT. Writing a 1 clears the corresponding bit in this
register. ERCE[3] corresponds to endpoint 3.
10.3.4.22 Endpoint Control Register 0 (EPCR0)
This register is not defined in the EHCI specification. Every device implements endpoint 0 as a control
endpoint.
Address: 0xFC0B_01C0 (EPCR0)
31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0 TXE 0 0 0
W
Reset 0 0 0 0 0 0 0 0
Field
31–24 Reserved, must be cleared.
23 TX endpoint enable. Endpoint zero is always enabled.
TXE 1 Enable
22–20 Reserved, must be cleared.
19–18 TX endpoint type. Endpoint zero is always a control endpoint.
TXT 00 Control
17 Reserved, must be cleared.
16 TX endpoint stall. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host.
TXS It continues returning STALL until software clears the bit or it automatically clears upon receipt of a new SETUP
request.
0 Endpoint OK
1 Endpoint stalled
15–8 Reserved, must be cleared.
7 RX endpoint enable. Endpoint zero is always enabled.
RXE 1 Enabled.
6–4 Reserved, must be cleared.
3–2 RX endpoint type. Endpoint zero is always a control endpoint.
RXT 00 Control
10-44
Table 10-40. EPCOMPLETE Field Descriptions (continued)
23 22 21 20 19 18 17
TXT
1 0 0 0 0 0 0
Figure 10-38. Endpoint Control 0 (EPCR0)
Table 10-41. EPCR0 Field Descriptions
Description
16 15 14 13 12 11 10
0 0 0 0 0 0 0 0 0 RXE 0 0 0 RXT 0
TXS
0 0 0 0 0 0 0 0 0
Description
Access: User read/write
9 8 7 6 5 4 3 2
1 0 0 0 0 0 0
Freescale Semiconductor
1 0
RXS
0