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31
31
SSI_RXD
Figure 27-13. Receive Data Path (RXBIT0=1, RSHFD=1) (lsb Alignment)
27.3.7
SSI Control Register (SSI_CR)
The SSI control register sets up the SSI modules. SSI operating modes are selected in this register (except
AC97 mode, which is selected in SSI_ACR register).
Address: 0xFC0B_C010 (SSI_CR)
31
30
29
R
0
0
0
W
Reset
0
0
0
15
14
13
R
0
0
0
W
Reset
0
0
0
Field
31–10
Reserved, must be cleared.
9
Clock idle state. Controls the idle state of the transmit clock port (SSI_BCLK and SSI_MCLK) during internal gated
CIS
clock mode.
0 Clock idle state is 1
1 Clock idle state is 0
8
Two channel operation enable. In this mode, two time slots are used out of the possible 32. Any two time slots (0 – 31)
TCH
can be selected by the mask registers. The data in the two time slots is alternately handled by the two data
registers (0 and 1). While receiving, RXSR transfers data to SSI_RX0 and SSI_RX1 alternately, and while
transmitting, data is alternately transferred from SSI_TX0 and SSI_TX1 to TXSR.
Two channel operation can be enabled for an even number of slots larger than two to optimize usage of both FIFOs.
However, TCH should be cleared for an odd number of time slots.
0 Two channel mode disabled
1 Two channel mode enabled
Freescale Semiconductor
23
19
16 bits
20 bits
24 bits
23
19
24 bits
20 bits
28
27
26
25
0
0
0
0
0
0
0
0
12
11
10
9
0
0
0
CIS
0
0
0
0
Figure 27-14. SSI Control Register (SSI_CR)
Table 27-7. SSI_CR Field Descriptions
15
11
12 bits
15
11
16 bits
12 bits
24
23
22
21
0
0
0
0
0
0
0
0
8
7
6
5
TCH
MCE
I2S
0
0
0
0
Description
Synchronous Serial Interface (SSI)
0
SSI_RX
0
RXSR
Access: User read/write
20
19
18
17
0
0
0
0
0
0
0
0
4
3
2
1
SYN
NET
RE
TE
0
0
0
0
16
0
0
0
SSI
_EN
0
27-13
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