Freescale Semiconductor MCF54455 Reference Manual page 917

Revision History
Chapter
Added notes regarding FlexBus signals tristating between bus cycles throughout.
Added footnote to FlexBus Signal Summary table regarding signal directions changing during PCI accesses.
Added indeterminate cycle at the end of the read cycle for address bus in all timing diagrams.
Added notes in basic read and basic write sections regarding this indeterminate cycle.
Corrected second sentence in CSMRn[WP] bit description.
Reworded first entry in results of address comparison table.
FlexBus
Rearranged FlexBus operating modes table.
Clarified first sentence in bus cycle states table, S1 Read entry. Moved second sentence into S2 Read entry.
Changed last sentence in first paragraph in memory map/register definition section from "Reading unused or
reserved locations terminates normally and returns zeros." to "Do not read unused or reserved locations."
Added notes in a few sections regarding the number of chip selects depends on the device and its pin configuration
Added note "When the MCF54450 and MCF54451 devices operate in non-multiplexed mode, only a 24-bit external
address is available, FB_A[23:0]" to beginning of chapter.
Added Read Clock Recovery (RCR) Block section.
SDRAM
Controller
Updated SD_DQS signal descriptions.
Changed ID reset value from 0x0041_FA05 to 0x0042_FA05
Corrected address offsets for the following registers:
CAPLENGTH from 0x0100 to 0x0103
HCIVERION from 0x0102 to 0x0100
DCIVERSION from 0x0120 to 0x0122
Corrected cross-reference in USBCMD[ATDTW] field description.
Moved USBCMD[ATDTW] from bit location 12 to bit 14. Bit 12 is reserved.
Changed reset value of FRINDEX from undefined to 0x0000_0000
Changed OTGSC[1MSS] reset value from 0 to 1.–
USB OTG
Added "This bit is self clearing," to EPCRn[TXR] and EPCRn[RXR] bit descriptions.
Swapped bit encodings in EPCRn[RXI] bit description.
Changed Total Bytes field to span bits 30–16 instead of 29–16 in Endpoint Transfer Descriptor (dTD) figure.
Added note to dTD Token[Total Bytes] field.
Figure USB 2.0 Device States: moved "when the host resets..." arrow from Attach state to Default FS/HS state.
Added note in Interrupt/Bulk Endpoint Operation section, in third bullet under "RX-dTD is complete when:"
Added second note to Software Link Pointers section.
Added the following dTD Token[Total Bytes] field description: "For OUT transfers the total bytes must be evenly
divisible by the maximum packet length."
PCI Added note at beginning of chapter: "The MCF54450 and MCF54451 devices only contain a 24-bit PCI_AD bus,
Controller PCI_AD[23:0]."
A-2
Table A-1. Rev. 2 to Rev. 3 Changes (continued)
Description
Freescale Semiconductor