Freescale Semiconductor MCF54455 Reference Manual page 478

In addition to address setup, a programmable address hold option for each chip select exists. Address and
attributes can be held one to four clocks after chip-select, byte-selects, and output-enable negate.
Figure 20-22 and Figure 20-23
FB_AD[23:0]
Mux'd Bus
FB_AD[31:X]
Non-Mux'd Bus
FB_D[31:X]
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TSIZ[1:0]
Figure 20-22. Read Cycle with Two-Clock Address Hold (No Wait States)
FB_AD[Y:0]
Mux'd Bus
FB_AD[31:X]
FB_A[23:0]
Non-Mux'd Bus
FB_D[31:X]
FB_CSn, FB_BE/BWEn
FB_TSIZ[1:0]
Figure 20-23. Write Cycle with Two-Clock Address Hold (No Wait States)
Freescale Semiconductor
show read and write bus cycles with two clocks of address hold.
S0
FB_CLK
ADDR[31:X]
FB_A[23:0]
ADDR[31:X]
FB_R/W
FB_ALE
FB_TA
S0
FB_CLK
ADDR[31:X]
ADDR[31:X]
FB_R/W
FB_ALE
FB_OE
FB_TA
S1 S2 AH
ADDR[23:0]
DATA
ADDR[23:0]
DATA
TSIZ[1:0]
S1 S2 AH
ADDR[Y:0]
DATA
ADDR[23:0]
DATA
TSIZ[1:0]
FlexBus
S3 S0
S3 S0
20-25