Transfer Burst (Fb_Tbst) - Freescale Semiconductor MCF54455 Reference Manual

for a longword write to an 8-bit port, FB_TSIZ[1:0] equals 00 for the first transaction and 01 for the next
three transactions. If bursting is used for longword write to an 8-bit port, FB_TSIZ[1:0] is driven to 00 for
the entire transfer.
20.2.8

Transfer Burst (FB_TBST)

Transfer burst indicates that a burst transfer is in progress as driven by the device. A burst transfer can be
two to 16 beats depending on FB_TSIZ[1:0] and the port size.
When burst (FB_TBST = 0), transfer size is 16 bytes (FB_TSIZ[1:0] = 11)
and the address is misaligned within the 16-byte boundary, the external
device must be able to wrap around the address.
20.2.9 Transfer Acknowledge (FB_TA)
This signal indicates the external data transfer is complete. When the processor recognizes FB_TA during
a read cycle, it latches the data and then terminates the bus cycle. When the processor recognizes FB_TA
during a write cycle, the bus cycle is terminated.
If auto-acknowledge is disabled (CSCRn[AA] = 0), the external device drives FB_TA to terminate the bus
transfer; if auto-acknowledge is enabled (CSCRn[AA] = 1), FB_TA is generated internally after a
specified number of wait states, or the external device may assert external FB_TA before the wait-state
countdown, terminating the cycle early. The device negates FB_CSn one cycle after the last FB_TA
asserts. During read cycles, the peripheral must continue to drive data until FB_TA is recognized. For write
cycles, the processor continues driving data one clock after FB_CSn is negated.
The number of wait states is determined by CSCRn or the external FB_TA input. If the external FB_TA is
used, the peripheral has total control on the number of wait states.
External devices should only assert FB_TA while the FB_CSn signal to the
external device is asserted.
Because this device shares the FlexBus signals with the PCI controller, this
signal tristates between bus cycles.
20.3 Memory Map/Register Definition
The following tables describe the registers and bit meanings for configuring chip-select operation.
Table 20-3 shows the chip-select register memory map.
The actual number of chip select registers available depends upon the device and its pin configuration. If
the device does not support certain chip select signals or the pin is not configured for a chip-select function,
then that corresponding set of chip-select registers has no effect on an external pin.
You must set CSMR0[V] before the chip select registers take effect.
Freescale Semiconductor
NOTE
NOTE
NOTE
FlexBus
20-5