Freescale Semiconductor MCF54455 Manuals

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Freescale Semiconductor MCF54455 Reference Manual

Freescale Semiconductor MCF54455 Reference Manual (921 pages)

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 11 MB

Table of Contents

Revision History

3
- Home Page
  5
- Table of Contents
  8
- About this Book
  30
- Audience
  30
- General Information
  30
- Suggested Reading
  30
- Coldfire Documentation
  31
- Conventions
  31
- Register Figure Conventions
  32
- Overview
  34
Chapter 1 Overview

34
- Mcf5445X Family Comparison
  34
- Block Diagram
  36
- Chip Level Features
  37
- Module-By-Module Feature List
  37
  - Version 4 Coldfire Variable-Length RISC Processor
    38
  - On-Chip Memories
    38
  - Phase Locked Loop (PLL)
    38
  - Power Management
    38
  - Chip Configuration Module (CCM)
    38
  - Reset Controller
    39
  - System Control Module
    39
  - Crossbar Switch
    39
  - Peripheral Component Interconnect (PCI) Bus
    39
  - Universal Serial Bus (USB) 2.0 On-The-Go (OTG) Controller
    39
  - DDR SDRAM Controller
    39
  - Flexbus (External Interface)
    40
  - Synchronous Serial Interface (SSI)
    40
  - ATA Controller
    40
  - Fast Ethernet Media Access Controller (FEC MAC)
    40
  - Random Number Generator (RNG)
    41
  - Real Time Clock
    41
  - Software Watchdog Timer
    41
  - Programmable Interrupt Timers (PIT)
    41
  - DMA Timers
    41
  - DMA Serial Peripheral Interface (DSPI)
    41
  - Universal Asynchronous Receiver Transmitters (Uarts)
    42
  - I2C Module
    42
  - Interrupt Controllers
    42
  - Edge Port Module
    42
  - DMA Controller
    42
  - General Purpose I/O Interface
    43
  - System Debug Support
    43
  - JTAG Support
    43
- Operating Parameters
  37
- Packages
  37
- Memory Map Overview
  43
  - Internal Peripheral Space
    44
- Documentation
  45
- Introduction
  46
- Signal Descriptions
  46
- Signal Properties Summary
  46
- Signal Primary Functions
  54
  - Reset Signals
    54
  - PLL and Clock Signals
    55
  - Mode Selection
    55
  - Flexbus Signals
    56
  - SDRAM Controller Signals
    57
  - PCI Controller Signals
    58
  - Serial Boot Facility Signals
    59
  - External Interrupt Signals
    59
  - DMA Signals
    59
  - Fast Ethernet Controller (FEC0 and FEC1) Signals
    59
  - I2C I/O Signals
    60
  - ATA Controller Signals
    61
  - DMA Serial Peripheral Interface (DSPI) Signals
    62
  - Synchronous Serial Interface (SSI) Signals
    62
  - Universal Serial Bus (USB) Signals
    63
  - UART Module Signals
    63
  - DMA Timer Signals
    64
  - Debug Support Signals
    64
  - Test Signals
    65
  - Power and Ground Pins
    66
- External Boot Mode
  66
Chapter 3 Coldfire Core

68
- Introduction
  68
  - Overview
    68
- Memory Map/Register Description
  71
  - Data Registers (D0-D7)
    73
  - Address Registers (A0-A6)
    74
  - Supervisor/User Stack Pointers (A7 and OTHER_A7)
    74
  - Condition Code Register (CCR)
    75
  - Program Counter (PC)
    76
  - Cache Programming Model
    76
  - MMU Programming Model
    76
  - Vector Base Register (VBR)
    76
  - Status Register (SR)
    77
  - Memory Base Address Register (RAMBAR)
    78
- Functional Description
  78
Chapter 4 Memory Management Unit (MMU)

102
- Introduction
  102
  - Block Diagram
    102
  - Features
    103
- Memory Map/Register Definition
  104
- Functional Description
  111
  - Virtual Memory Management Architecture
    112
  - Acr Address Improvements
    115
  - Debugging in a Virtual Environment
    116
  - Virtual Memory Architecture Processor Support
    116
  - Access Error Stack Frame Additions
    117
  - Effective Address Attribute Determination
    118
  - MMU Functionality
    119
  - Mmu Tlb
    119
  - MMU Operation
    119
  - MMU Implementation
    121
    
    Tlb Address Fields
    121
    
    Tlb Replacement Algorithm
    122
    
    Tlb Locked Entries
    123
  - MMU Instructions
    124
Chapter 5 Enhanced Multiply-Accumulate Unit (EMAC)

126
- Introduction
  126
  - Overview
    126
- Memory Map/Register Definition
  128
- Functional Description
  133
  - Fractional Operation Mode
    135
  - EMAC Instruction Set Summary
    137
  - EMAC Instruction Execution Times
    138
  - Data Representation
    139
  - MAC Opcodes
    139
Chapter 6 Cache

146
- Introduction
  146
  - Block Diagram
    146
  - Overview
    146
- Cache Organization
  147
  - Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified
    148
  - The Cache at Start-Up
    148
- Memory Map/Register Definition
  150
  - Cache Control Register (CACR)
    150
  - Access Control Registers (Acrn)
    153
- Functional Description
  154
  - Caching Modes
    157
  - Cache Protocol
    159
  - Read Hit
    160
  - Cache Coherency (Data Cache Only)
    161
  - Memory Accesses for Cache Maintenance
    161
  - Cache Locking
    162
  - Cache Management
    164
  - Cache Operation Summary
    166
  - Instruction Cache State Transitions
    166
  - CPUSHL Enhancements
    170
- Initialization/Application Information
  172
Chapter 7 Static RAM (SRAM)

174
- Introduction
  174
- Memory Map/Register Description
  175
- Sram Initialization Code
  177
  - Power Management
    178
    
    Introduction
    180
    
    Block Diagram
    182
Chapter 11

183
- Modes of Operation
  183
- Memory Map/Register Definition
  184
Chapter 8

185
- PLL Control Register (PCR)
  185
- PLL Status Register (PSR)
  187
- Functional Description
  188
- Lock Conditions
  189
- System Clock Modes
  190
- Clock Operation During Reset
  191
- Introduction
  192
Chapter 9

193
- Wake-Up Control Register (WCR)
  193
- Peripheral Power Management Set Register (PPMSR0)
  194
- Peripheral Power Management Clear Register (PPMCR0)
  195
- Low-Power Control Register (LPCR)
  198
- Peripheral Shut down
  199
- Peripheral Behavior in Low-Power Modes
  200
- Summary of Peripheral State During Low-Power Modes
  205
  - Introduction
    208
  - Block Diagram
    209
  - Features
    210
  - Modes of Operation
    211
  - External Signal Description
    212
Chapter 10

213
- USB OTG Control and Status Signals
  213
- Memory Map/Register Definition
  214
- Module Identification Registers
  216
- Device/Host Timer Registers
  220
- Capability Registers
  221
- Operational Registers
  225
- System Interface
  254
- Initialization/Application Information
  255
- Device Data Structures
  256
- Device Operation
  263
- Servicing Interrupts
  281
- Deviations from the EHCI Specifications
  282
- Introduction
  288
- External Signal Descriptions
  289
- Chip Configuration Register (CCR)
  290
- Reset Configuration Register (RCON)
  294
- Chip Identification Register (CIR)
  295
- Clock-Divider Register (CDR)
  298
  - Reset Configuration
    300
  - Boot Configuration
    306
  - Low Power Configuration
    307
    
    Introduction
    308
    
    Features
    309
Chapter 12

310
- Serial Boot Facility Status Register (SBFSR)
  310
- Functional Description
  311
- Reset Configuration and Optional Boot Load
  312
- Execution Transfer
  313
- FAST_READ Feature Initialization
  314
  - Introduction
    316
  - External Signal Description
    317
- Reset Status Register (RSR)
  318
- Reset Sources
  319
- Reset Control Flow
  320
- Concurrent Resets
  322
- Introduction
  324
- Master Privilege Register (MPR)
  325
- Peripheral Access Control Registers (Pacrx)
  327
- Core Watchdog Control Register (CWCR)
  330
- Core Watchdog Service Register (CWSR)
  331
- SCM Interrupt Status Register (SCMISR)
  332
- Burst Configuration Register (BCR)
  333
- Core Fault Interrupt Enable Register (CFIER)
  334
- Core Fault Attributes Register (CFATR)
  335
- Access Control
  336
- Core Data Fault Recovery Registers
  337
  - Overview
    338
  - Features
    340
Chapter 15

341
- XBS Priority Registers (Xbs_Prsn)
  341
- XBS Control Registers (Xbs_Crsn)
  342
  - Functional Description
    344
  - Initialization/Application Information
    345
  - Introduction
    346
Chapter 26

348
- Overview
  348
- Memory Map/Register Definition
  357
- Port Output Data Registers (Podr_X)
  361
- Port Data Direction Registers (Pddr_X)
  363
- Port Pin Data/Set Data Registers (Ppdsdr_X)
  365
- Port Clear Output Data Registers (Pclrr_X)
  368
- Pin Assignment Registers (Par_X)
  370
- SDRAM Mode Select Control Register (MSCR_SDRAM)
  383
- PCI Mode Select Control Register (MSCR_PCI)
  384
  - Functional Description
    387
  - Initialization/Application Information
    388
  - Introduction
    390
  - Memory Map/Register Definition
    391
Chapter 17

393
Chapter 29

411
- Low-Power Mode Operation
  411
Chapter 18

412
- EPORT Pin Assignment Register (EPPAR)
  412
- EPORT Data Direction Register (EPDDR)
  413
- Edge Port Interrupt Enable Register (EPIER)
  414
- Edge Port Flag Register (EPFR)
  415
  - Overview
    416
  - Features
    417
Chapter 19

418
- Debug Mode
  418
- Memory Map/Register Definition
  419
- Edma Error Status Register (EDMA_ES)
  420
- Edma Enable Request Register (EDMA_ERQ)
  423
- Edma Enable Error Interrupt Registers (EDMA_EEI)
  424
- Edma Set Enable Request Register (EDMA_SERQ)
  425
- Edma Set Enable Error Interrupt Register (EDMA_SEEI)
  426
- Edma Clear Interrupt Request Register (EDMA_CINT)
  427
- Edma Clear Error Register (EDMA_CERR)
  428
- Edma Clear DONE Status Bit Register (EDMA_CDNE)
  429
- Edma Interrupt Request Register (EDMA_INT)
  430
- Edma Channel N Priority Registers (Dchprin)
  431
- Transfer Control Descriptors (Tcdn)
  432
- Functional Description
  439
- Edma Basic Data Flow
  440
- Initialization/Application Information
  443
- DMA Programming Errors
  446
- DMA Transfer
  447
- Edma Tcdn Status Monitoring
  450
- Channel Linking
  451
- Dynamic Programming
  452
- Introduction
  454
- External Signals
  455
  - Address and Data Buses (Fb_An, Fb_Dn, Fb_Adn)
    456
  - Read/Write (FB_R/W)
    457
  - Transfer Burst (FB_TBST)
    458
  - Chip-Select Address Registers (CSAR0 – CSAR5)
    459
  - Chip-Select Mask Registers (CSMR0 – CSMR5)
    460
    
    Functional Description
    463
    
    Data Transfer Operation
    464
  - Data Byte Alignment and Physical Connections
    465
  - Bus Cycle Execution
    466
  - Data Transfer Cycle States
    467
  - Flexbus Timing Examples
    467
    
    Basic Read Bus Cycle
    468
    
    Basic Write Bus Cycle
    469
    
    Timing Variations
    474
  - Burst Cycles
    479
  - Misaligned Operands
    487
  - Bus Errors
    487
  - Introduction
    488
Chapter 35

489
- Block Diagram
  489
Chapter 21 Terminology

490
- Interface Recommendations
  492
  - Supported Memory Configurations
    492
  - Sdram Ddr Component Connections
    495
  - Ddr Sdram Layout Considerations
    495
  - Termination Example
    496
- SDRAM Mode/Extended Mode Register (SDMR)
  497
- SDRAM Control Register (SDCR)
  498
- SDRAM Configuration Register 1 (SDCFG1)
  499
- SDRAM Configuration Register 2 (SDCFG2)
  502
- SDRAM Chip Select Configuration Registers (Sdcsn)
  503
- Sdram Commands
  504
- Read Clock Recovery (RCR) Block
  513
- Initialization/Application Information
  514
- Low-Power/Mobile SDRAM Initialization Sequence
  515
- Page Management
  516
- Transfer Size
  517
  - Introduction
    518
  - Features
    519
Chapter 13 External Signal Description

520
Chapter 22

521
- Device Select (PCI_DEVSEL)
  521
- Reset (PCI_RST)
  522
- Pci Type 0 Configuration Registers
  524
- General Control/Status Registers
  531
- PCI Arbiter Registers
  542
- Functional Description
  544
  - Pci Bus Protocol
    545
    
    Pci Bus Background
    545
    
    Pci Bus Commands
    548
  - Configuration Interface
    552
  - Internal Bus Initiator Interface
    553
    
    Endian Translation
    554
    
    Configuration Mechanism
    555
    
    Special Cycle Transactions
    558
  - Internal Bus Target Interface
    559
  - Reads from Local Memory
    560
  - Pci Arbiter
    563
    
    Arbitration Latency
    565
    
    Arbitration Examples
    565
    
    Bus Parking
    567
  - Pci Clock Scheme
    569
- Application Information
  570
  - Address Translation
    571
    
    Inbound Address Translation
    571
    
    Outbound Address Translation
    573
    
    Base Address Register Overview
    573
    
    Introduction
    576
    
    Features
    577
    
    External Signal Description
    578
Chapter 23

579
- Detailed Signal Descriptions
  579
- Memory Map/Register Definition
  580
- Endianness
  581
- Timing Registers (Time_X)
  582
- FIFO_FILL Register
  583
- Interrupt Registers
  584
- FIFO Alarm Register (FIFO_ALARM)
  587
- Functional Description
  588
  - Resetting ATA Bus
    596
  - Using DMA Mode to Transmit Data to ATA Bus
    598
- Introduction
  602
- Features
  603
  - CAU Status Register (CASR)
    604
  - Programming Model
    605
  - Coprocessor Instructions
    605
  - CAU Commands
    606
- Application/Initialization Information
  611
Chapter 14

613
- Introduction
  613
- Memory Map/Register Definition
  614
Chapter 25

615
- RNG Status Register (RNGSR)
  615
- RNG Entropy Register (RNGER)
  616
  - Functional Description
    617
  - Initialization/Application Information
    618
  - Introduction
    619
  - Block Diagram
    620
  - Features
    621
- Full and Half Duplex Operation
  622
- Interface Options
  622
- Address Recognition Options
  623
- Internal Loopback
  623
- Memory Map/Register Definition
  624
- Mib Block Counters Memory Map
  626
- Buffer Descriptors
  647
  - Initialization Sequence
    652
- Microcontroller Initialization
  653
- Network Interface Options
  654
- Fec Frame Transmission
  655
- Ethernet Address Recognition
  657
- Fec Frame Reception
  657
- Hash Algorithm
  660
- Full Duplex Flow Control
  663
- Inter-Packet Gap (IPG) Time
  664
- RMII Loopback
  665
  - Introduction
    668
  - Overview
    669
Chapter 16

670
- Features
  670
- External Signal Description
  672
- SSI_TXD — Serial Transmit Data
  673
- Memory Map/Register Definition
  674
Chapter 27

675
Chapter 28

725
- RTC Seconds Counter Register (RTC_SECONDS)
  725
- RTC Seconds Alarm Register (RTC_ALRM_SEC)
  726
- RTC Control Register (RTC_CR)
  727
- RTC Interrupt Enable Register (RTC_IER)
  728
- RTC Stopwatch Minutes Register (RTC_STPWCH)
  730
- RTC General Oscillator Clock Upper Register (RTC_GOCU)
  731
- Functional Description
  732
- Alarm
  733
- Minute Stopwatch
  734
  - Introduction
    736
  - Memory Map/Register Definition
    737
- PIT Control and Status Register (Pcsrn)
  738
- PIT Modulus Register (Pmrn)
  740
- Functional Description
  741
- Timeout Specifications
  742
  - Introduction
    743
  - Features
    744
  - Memory Map/Register Definition
    745
Chapter 30

747
- DMA Timer Extended Mode Registers (Dtxmrn)
  747
- DMA Timer Reference Registers (Dtrrn)
  749
- Capture Mode
  750
- Output Mode
  751
- Calculating Time-Out Values
  752
  - Introduction
    754
  - Features
    755
  - Modes of Operation
    756
  - External Signal Description
    757
- Serial Input (DSPI_SIN)
  758
- DSPI Transfer Count Register (DSPI_TCR)
  761
- DSPI Status Register (DSPI_SR)
  767
- DSPI Dma/Interrupt Request Select and Enable Register (DSPI_RSER)
  769
- DSPI Push Transmit FIFO Register (DSPI_PUSHR)
  770
- DSPI Pop Receive FIFO Register (DSPI_POPR)
  772
- DSPI Receive FIFO Registers 0–15 (Dspi_Rxfrn)
  773
- Start and Stop of Dspi Transfers
  774
- Serial Peripheral Interface (SPI) Configuration
  775
- Dspi Baud Rate and Clock Delay Generation
  778
- Transfer Formats
  781
- Continuous Serial Communications Clock
  787
- Interrupts/Dma Requests
  788
- Power Saving Features
  790
- Baud Rate Settings
  791
- How to Change Queues
  791
- Delay Settings
  792
- Calculation of Fifo Pointer Addresses
  793
  - Introduction
    795
  - Features
    796
  - External Signal Description
    797
Chapter 32

799
- UART Mode Registers 1 (Umr1N)
  799
- UART Mode Register 2 (Umr2N)
  800
- UART Status Registers (Usrn)
  802
- UART Clock Select Registers (Ucsrn)
  803
- UART Receive Buffers (Urbn)
  805
- UART Transmit Buffers (Utbn)
  806
- UART Auxiliary Control Register (Uacrn)
  807
- UART Baud Rate Generator Registers (Ubg1N/Ubg2N)
  809
- UART Output Port Command Registers (Uop1N/Uop0N)
  810
  - Transmitter and Receiver Operating Modes
    812
  - Looping Modes
    816
  - Multidrop Mode
    817
  - Bus Operation
    819
  - Interrupt and DMA Request Initialization
    820
  - UART Module Initialization Sequence
    821
  - Introduction
    827
Chapter 31

828
- Overview
  828
- Memory Map/Register Definition
  829
Chapter 33

833
- Start Signal
  833
- Slave Address Transmission
  834
- Data Transfer
  834
- Stop Signal
  835
- Repeated Start
  835
- Clock Synchronization and Arbitration
  837
- Handshaking and Clock Stretching
  838
- Generation of Stop
  839
- Generation of Repeated Start
  840
- Slave Mode
  840
- Arbitration Lost
  840
- Introduction
  844
Chapter 2 Signal Descriptions

846
- Processor Status/Debug Data (PSTDDATA[7:0])
  847
- Memory Map/Register Definition
  848
- Shared Debug Resources
  850
- Configuration/Status Register (CSR)
  851
- BDM Address Attribute Register (BAAR)
  853
- Address Attribute Trigger Registers (AATR, AATR1)
  854
- Trigger Definition Register (TDR)
  856
- Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR)
  859
- PC Breakpoint ASID Control Register (PBAC)
  860
- Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1)
  861
- Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1)
  862
- PC Breakpoint ASID Register (PBASID)
  863
- Extended Trigger Definition Register (XTDR)
  864
  - Resulting Set of Possible Trigger Combinations
    867
  - Functional Description
    868
  - Receive Packet Format
    871
  - Command Sequence Diagrams
    873
- Real-Time Debug Support
  891
- Concurrent Bdm and Processor Operation
  894
  - User Instruction Set
    899
  - Supervisor Instruction Set
    904
- Freescale-Recommended BDM Pinout
  905
  - Introduction
    906
  - Features
    907
- Test Clock Input (TCLK)
  908
- Test Reset/Development Serial Clock (TRST/DSCLK)
  909
- Idcode Register
  910
- Bypass Register
  910
- Boundary Scan Register
  911
- Jtag Module
  911
- Tap Controller
  911
- Jtag Instructions
  912
- Idcode Instruction
  913
- Nonscan Chain Operation
  915
Appendix A Revision History

916

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