Concurrent Bdm And Processor Operation - Freescale Semiconductor MCF54455 Reference Manual

• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is
negated and the processor begins reset exception processing. It can be set while the processor is
halted before reset exception processing begins. See
• A debug interrupt always puts the processor in emulation mode when debug interrupt exception
processing begins.
• Setting CSR[TRC] forces the processor into emulation mode when trace exception processing
begins.
While operating in emulation mode, the processor exhibits the following properties:
• Unmasked interrupt requests are serviced. The resulting interrupt exception stack frame has FS set
appropriately (0010) to indicate the interrupt occurred while in emulator mode.
• If CSR[MAP] is set, all caching of memory and the SRAM module are disabled. All memory
accesses are forced into a specially mapped address space signaled by TT equals 0x2,
TM equals 0x5, or 0x6. This includes stack frame writes and vector fetch for the exception that
forced entry into this mode.
The RTE instruction exits emulation mode. The processor status output port provides a unique encoding
for emulator mode entry (0xD) and exit (0x7).
34.4.3

Concurrent BDM and Processor Operation

The debug module supports concurrent operation of the processor and most BDM commands. BDM
commands may be executed while the processor is running, except these following operations that access
processor/memory registers:
• Read/write address and data registers
• Read/write control registers
For BDM commands that access memory, the debug module requests the processor's local bus. The
processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to
complete before freeing the local bus for the debug module to perform its access. After the debug module
bus cycle, the processor reclaims the bus.
Breakpoint registers must be carefully configured in a development system
if the processor is executing. The debug module contains no hardware
interlocks, so TDR and XTDR should be disabled while breakpoint registers
are loaded, after which TDR and XTDR can be written to define the exact
trigger. This prevents spurious breakpoint triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU
is writing the debug's registers (DSCLK must be inactive).
34.4.4 Real-Time Trace Support
Real-time trace, which defines the dynamic execution path and is also known as instruction trace, is a
fundamental debug function. The ColdFire solution is to include a parallel output port providing encoded
Freescale Semiconductor
Section 34.4.1.1, "CPU
NOTE
Debug Module
Halt".
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