Freescale Semiconductor MCF54455 Reference Manual page 786

DSPI_SCK
(CPOL = 0)
DSPI_SCK
(CPOL = 1)
Master DSPI_SOUT
Master DSPI_SIN
DSPI_PCSn
t
CSC
t
ASC
t
DT
Figure 31-19. Example of Non-Continuous Format (CPHA=1, CONT=0)
When CONT is set and the DSPI_PCSn signal for the next transfer the same as for the current transfer,
DSPI_PCSn signal remains asserted for the duration of the two transfers. The delay between transfers (t
is not inserted between the transfers.
CPHA and CONT set.
DSPI_SCK
(CPOL = 0)
DSPI_SCK
(CPOL = 1)
Master DSPI_SOUT
Master DSPI_SIN
DSPI_PCSn
t
CSC
t
ASC
Figure 31-20. Example of Continuous Transfer (CPHA = 1, CONT = 1)
In Figure 31-20, the period length at the start of the next transfer is the sum of t
include a half-clock period. The default settings for these provide a total of four system clocks. In many
situations, t and t
ASC CSC
Switching DSPI_CTARn registers between frames while using continuous selection can cause errors in
the transfer. The DSPI_PCSn signal must be negated before DSPI_CTAR is switched.
When CONT is set and the DSPI_PCSn signals for the next transfer are different from the present transfer,
the DSPI_PCSn signals behave as if the CONT bit was cleared.
Freescale Semiconductor
t t
CSC ASC
= PCS to SCK delay.
= After SCK delay.
= Delay after transfer (minimum CS negation time).
Figure 31-20
t t
CSC ASC
= PCS to SCK delay.
= After SCK delay.
must be increased if a full half-clock period is required.
t
DT
t
CSC
shows the timing diagram for two four-bit transfers with
t
CSC
DMA Serial Peripheral Interface (DSPI)
and t . It does not
ASC CSC
)
DT
31-33