Freescale Semiconductor MCF54455 Reference Manual page 89

ColdFire Core
0x0000_0004 is loaded into the program counter. After the initial instruction is fetched from memory,
program execution begins at the address in the PC. If an access error or address error occurs before the first
instruction is executed, the processor enters the fault-on-fault state.
ColdFire processors load hardware configuration information into the D0 and D1 general-purpose
registers after system reset. The hardware configuration information is loaded immediately after the
reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM
to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in
BDM: Load: 0x080 (D0)
Store: 0x180 (D0)
31 30 29
R
W
Reset 1 1 0
15 14 13
R MAC DIV EMAC FPU
W
Reset 0 1 1
Table 3-9. D0 Hardware Configuration Info Field Description
Field
31–24 Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present.
PF
23–20 ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core.
VER 0001 V1 ColdFire core
0010 V2 ColdFire core
0011 V3 ColdFire core
0100 V4 ColdFire core (This is the value used for this device.)
0101 V5 ColdFire core
Else Reserved for future use
19–16 Processor revision number. The default is 0b0010.
REV
15 MAC present. This bit signals if the optional multiply-accumulate (MAC) execution engine is present in processor core.
MAC 0 MAC execute engine not present in core. (This is the value used for this device.)
1 MAC execute engine is present in core.
14 Divide present. This bit signals if the hardware divider (DIV) is present in the processor core.
DIV 0 Divide execute engine not present in core.
1 Divide execute engine is present in core.
13 EMAC present. This bit signals if the optional enhanced multiply-accumulate (EMAC) execution engine is present in
EMAC processor core.
0 EMAC execute engine not present in core.
1 EMAC execute engine is present in core. (This is the value used for this device.)
3-23
28 27 26 25
PF
0 1 1 1
12 11 10 9
0 0 0
0 0 0 0
Figure 3-12. D0 Hardware Configuration Info
Description
(This is the value used for this device.)
24 23 22 21
VER
1 0 1 0
8 7 6 5
0 ISA
0 0 0 1
Figure 3-12.
Access: User read-only
BDM read-only
20 19 18 17
REV
0 0 0 1
4 3 2 1
DEBUG
0 1 0 1
Freescale Semiconductor
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0
0
1