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Crossbar Switch (XBS)
Address
0xFC00_4300 Priority Register Slave 3 (XBS_PRS3)
0xFC00_4310 Control Register Slave 3 (XBS_CRS3)
0xFC00_4400 Priority Register Slave 4 (XBS_PRS4)
0xFC00_4410 Control Register Slave 4 (XBS_CRS4)
0xFC00_4500 Priority Register Slave 5 (XBS_PRS5)
0xFC00_4510 Control Register Slave 5 (XBS_CRS5)
0xFC00_4700 Priority Register Slave 7 (XBS_PRS7)
0xFC00_4710 Control Register Slave 7 (XBS_CRS7)
15.4.1
XBS Priority Registers (XBS_PRSn)
The priority registers (XBS_PRSn) set the priority of each master port on a per slave port basis and reside
in each slave port. The priority register can be accessed only with 32-bit accesses. After the
XBS_CRSn[RO] bit is set, the XBS_PRSn register can only be read; attempts to write to it have no effect
on XBS_PRSn and result in a bus-error response to the master initiating the write.
Additionally, no two available master ports may be programmed with the same priority level, including
reserved masters. Attempts to program two or more masters with the same priority level result in a
bus-error response (see
Section 14.2.5, "SCM Interrupt Status Register
is not updated.
Address: 0xFC00_4100 (XBS_PRS1)
0xFC00_4200 (XBS_PRS2)
0xFC00_4300 (XBS_PRS3)
0xFC00_4400 (XBS_PRS4)
0xFC00_4500 (XBS_PRS5)
0xFC00_4700 (XBS_PRS7)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0
M7
W
Reset 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
15-4
Table 15-2. XBS Memory Map (continued)
Register
0
0
0 0 0 0 0
M6
M5
Figure 15-2. XBS Priority Registers Slave n (XBS_PRSn)
Width
Access Reset Value Section/Page
(bits)
32
R/W
0x6540_3210
32
R/W
0x0000_0000
32
R/W
0x6540_3210
32
R/W
0x0000_0000
32
R/W
0x6540_3210
32
R/W
0x0000_0000
32
R/W
0x6540_3210
32
R/W
0x0000_0000
(SCMISR)") and the XBS_PRSn
Access: Supervisor read/write
8
7
6
5
0
0
M3
M2
M1
Freescale Semiconductor
15.4.1/15-4
15.4.2/15-5
15.4.1/15-4
15.4.2/15-5
15.4.1/15-4
15.4.2/15-5
15.4.1/15-4
15.4.2/15-5
4
3
2
1
0
0
M0
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