Edma Enable Error Interrupt Registers (Edma_Eei) - Freescale Semiconductor MCF54455 Reference Manual

Channel
10
11
12
13
14
15
1
For information on how to select between SSI and Timer sources, refer to
Chapter 11, "Chip Configuration Module (CCM)."
As a given channel completes the processing of its major iteration count, a flag in the transfer control
descriptor that affect the ending state of the EDMA_ERQ bit for that channel. If the TCDn_CSR[D_REQ]
bit is set, the corresponding EDMA_ERQ bit is cleared, disabling the DMA request. If the D_REQ bit
clears, the state of the EDMA_ERQ bit is unaffected.
19.4.4

eDMA Enable Error Interrupt Registers (EDMA_EEI)

The EDMA_EEI register provides a bit map for the 16 channels to enable the error interrupt signal for each
channel. The state of any given channel's error interrupt enable is directly affected by writes to this
register; it is also affected by writes to the EDMA_SEEI and EDMA_CEEI. The EDMA_{S,C}EEIR are
provided so the error interrupt enable for a single channel can easily be modified without the need to
perform a read-modify-write sequence to the EDMA_EEI register.
The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt
request for a given channel is asserted to the interrupt controller.
Address: 0xFC04_4016 (EDNA_EEI)
15 14 13
R
EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI9
W
Reset 0 0 0
Figure 19-6. eDMA Enable Error Interrupt Register (EDMA_EEI)
Field
15–0 Enable error interrupt n.
EEIn 0 The error signal for channel n does not generate an error interrupt.
1 The assertion of the error signal for channel n generates an error interrupt request.
Freescale Semiconductor
Table 19-6. DMA Request Summary for eDMA (continued)
Source
DTER2[CAP] or DTER2[REF] /
SSISR[TFE0]
DTER3[CAP] or DTER3[REF] /
SSISR[TFE1]
DSPI_SR[RFDF]
DSPI_SR[TFFF]
ATA_ISR[DMA]
ATA_ISR[DMA]
12 11 10 9
0 0 0 0
Table 19-7. EDMA_EEI Field Descriptions
Enhanced Direct Memory Access (eDMA)
Description
Timer 2 / SSI0 Transmit
Timer 3 / SSI1 Transmit
DSPI Receive
DSPI Transmit
ATA Receive
ATA Transmit
8 7 6 5
EEI8 EEI7 EEI6 EEI5
0 0 0 0
Description
1
1
Access: User read/write
4 3 2 1
EEI4 EEI3 EEI2 EEI1
0 0 0 0
0
EEI0
0
19-9