Pci Controller Signals - Freescale Semiconductor MCF54455 Reference Manual

2.3.6

PCI Controller Signals

Table 2-8 describes the external interrupt signals used on the external PCI bus.
Signal Name
PCI Address/Data Bus PCI_AD[31:0] Multiplexed address/data bus.
PCI Command/Byte
Enables
PCI Device Select
PCI Frame
PCI External Bus Grant PCI_GNT[3:1] Asserted to an external master to give it control of PCI bus. If internal
PCI External Bus
Grant/Request
PCI Initialization Device
Select
PCI Initiator Ready
PCI Parity
PCI Parity Error
PCI External Bus
Request
PCI External Bus
Request/Grant
PCI Reset
PCI System Error
PCI Stop
PCI Target Ready
PCI Interrupt A
Freescale Semiconductor
Table 2-8. PCI Controller Signals
Abbreviation
PCI_CBE[3:0] Multiplexed PCI command and byte enables. The PCI command is
present during address phase; the byte enables are present during
data phase.
PCI_DEVSEL Indicates processor has recognized itself as the target of a PCI
transaction from address presented on the PCI bus.
PCI_FRAME Asserted by a PCI initiator to indicate the beginning of a transaction.
It is negated when initiator is ready to complete final data phase.
PCI arbiter is enabled, it asserts one of the PCI_GNT[3:1] signals to
grant ownership of PCI bus to external master. When PCI arbiter is
disabled, PCI_GNT[3:1] are driven high and should be ignored.
PCI_GNT0/ Asserted to external master device 0 to give it control of the PCI bus.
PCI_EXTREQ When the PCI arbiter is disabled, the signal operates as the
PCI_EXTREQ output, which is asserted when the processor needs to
initiate a PCI transaction.
PCI_IDSEL Asserted during a PCI type-0 configuration cycle to address the PCI
configuration header.
PCI_IRDY Indicates that PCI initiator is ready to transfer data. During a write
operation, assertion indicates the master is driving valid data on bus.
During a read operation assertion indicates that master is ready to
accept data.
PCI_PAR Indicates the parity of the data on the PCI_AD[31:0] and
PCI_CBE[3:0] signals.
PCI_PERR Asserted when data phase parity error is detected if enabled.
PCI_REQ[3:1] Asserted by an external PCI master when it requires access to the PCI
bus.
PCI_REQ0/ Asserted by external PCI master device 0 when it requires access to
PCI_EXTGNT the PCI bus. When internal PCI arbiter is disabled, this signal is used
as a grant input for PCI bus, which is driven by an external PCI arbiter.
PCI_RST Asserted by processor to reset PCI bus. It is asserted when processor
is reset and must be negated to enable usage on PCI bus.
PCI_SERR Indicates detection of an address-phase-parity error.
PCI_STOP Indicates that the currently addressed target wishes to stop the
current transaction.
PCI_TRDY Indicates currently addressed target is ready to complete the current
data phase.
PCI_INTA This output is the PCI interrupt A signal.
Function
Signal Descriptions
I/O
I/O
I/O
O
I/O
O
O
O
I/O
I/O
I/O
I
I
O
I/O
I/O
I/O
O
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