Wake-Up Control Register (Wcr) - Freescale Semiconductor MCF54455 Reference Manual

Power Management
9.2.1

Wake-up Control Register (WCR)

Implementation of low-power stop mode and exit from a low-power mode via an interrupt requires
communication between the core and logic associated with the interrupt controller. The WCR enables
entry into low-power modes and includes the interrupt level setting needed to exit a low-power mode.
The setting of the low-power mode select field, WCR[LPMD], determines
which low-power mode the device enters when a STOP instruction is issued.
Sequence of operations generally needed to enable this functionality:
1. The WCR register is programmed, setting the ENBWCR bit and the desired interrupt priority level.
2. At the appropriate time, the processor executes the privileged STOP instruction. After the
processor stops execution, it asserts a specific processor status (PST) encoding. Issuing the STOP
instruction when the WCR[ENBWCR] is set causes the SCM to enter the mode specified in
WCR[LPMD].
3. The low power mode control logic processes the entry into a low power mode, and the appropriate
clocks (usually those related to the high-speed processor core) are disabled.
4. After entering the low-power mode, the interrupt controller enables a combinational logic path
which evaluates any unmasked interrupt requests. The device waits for an event to generate an
interrupt request with a priority level greater than the value programmed in WCR[PRILVL].
5. After an appropriately high interrupt request level arrives, the interrupt controller signals its
presence, and the SCM responds by asserting the request to exit low-power mode.
6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks.
7. With the processor clocks enabled, the core processes the pending interrupt request.
Address: 0xFC04_0013 (WCR)
7
R
ENBWCR
W
Reset: 0
Field
7 Enable low-power mode entry. The mode entered is specified in WCR[LPMD].
ENBWCR 0 Low-power mode entry is disabled
1 Low-power mode entry is enabled.
6 Reserved, must be cleared.
9-2
NOTE
6 5 4
0
LPMD
0 0 0
Figure 9-1. Wake-up Control Register (WCR)
Table 9-2. WCR Field Descriptions
Description
Access: Supervisor read/write
3 2 1
0
PRILVL
0 0 0
Freescale Semiconductor
0
0