Freescale Semiconductor MCF54455 Reference Manual page 483

FlexBus
Figure 20-28 shows a longword write to an 8-bit device with burst inhibited. The transfer results in four
individual transfers. The transfer size is driven at longword (00) during the first transfer and at byte (01)
during the next three transfers.
S0
FB_CLK
FB_AD[23:0]
ADDR
FB_AD[31:24]
[31:24]
FB_A[23:0]
ADDR
FB_D[31:24]
[31:24]
FB_R/W
FB_ALE
FB_CSn,
FB_BE/BWEn
FB_TBST, FB_OE
FB_TA
FB_TSIZ[1:0]
Figure 20-28. Longword-Write Burst-Inhibited to 8-Bit Port (No Wait States)
Figure 20-29 illustrates another read burst transfer, but in this case a wait state is added between individual
beats.
CSCRn[WS] determines the number of wait states in the first beat.
However, for subsequent beats, the CSCRn[WS] (or CSCRn[SWS] if
CSCRn[SWSEN] is set) determines the number of wait states.
20-30
AS S1 S2 S0 AS S1
ADDR[23:0]
DATA
ADDR[23:0]
ADDR + 1
DATA
00
NOTE
S2 S0 AS S1 S2
DATA DATA
ADDR + 2
DATA DATA
01 01
S0 AS S1 S2 S0
S3
DATA
DATA
ADDR + 3
DATA
DATA
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