Freescale Semiconductor MCF54455 Reference Manual page 494

Table 21-3. SDRAM-Address Multiplexing in 16-bit Bus Mode (continued)
Device Configuration
32 M x 16 bit
512 Mbits
64M x 8bit
1 Gbits 64M x 16bit
2 Gbits 128M x16bit
1
All SD_A[13:0] bits are generated on every access, but only the bits actually used by the memory are shown.
2
All column address (CA) bits in this table are physical column address lines. The SDRAM controller inserts an
extra bit CA10 to control the precharge option.
All memory devices of a single chip-select block must have the same configuration and row/column
address width; however, this is not necessary between different blocks. If mixing different memory
organizations in different blocks, the following guidelines ensure that every block is fully contiguous.
If all devices' row address width is 12 bits, the column address can be  9 bits.
•
If all devices' row address width is 13 bits, the column address can be  9 bits.
•
If all devices' column address width is 9 bits, the row address can be  11 bits.
•
• The maximum row bits plus column bits equals 25.
• x16 data width memory devices cannot be mixed with any other width.
Freescale Semiconductor
Row bit x SDCR
Col bit x [ADDR_
Banks MUX] 27
12 x 11 x 4 00 —
13 x 10 x 4 01 —
14 x 9 x 4 10 —
12 x 12 x 4 00 —
13 x 11 x 4 01 —
14 x 10 x 4 10 —
12 x 12 x 4 00 —
13 x 11 x 4 01 —
14 x 10 x 4 10 —
12 x 13 x 4 00 CA13
13 x 12 x 4 01 CA12
14 x 11 x 4 10 CA11
Internal Address
26 25 24 23 – 12 11 – 10
— CA11 CA9
— CA9 RA12
— RA13 RA12
RA11-0 BA1-0
CA12 CA11 CA9
CA11 CA9 RA12
CA9 RA13 RA12
CA12 CA11 CA9
CA11 CA9 RA12 RA11-0 BA1-0
CA9 RA13 RA12
CA12 CA11 CA9
CA11 CA9 RA12 RA11-0 BA1-0
CA9 RA13 RA12
SDRAM Controller (SDRAMC)
9 – 1
CA8-0
CA8-0
CA8-0
21-7