Peripheral Behavior In Low-Power Modes - Freescale Semiconductor MCF54455 Reference Manual

9.3.3.2 Wait Mode
Wait mode is intended to stop only the CPU and memory clocks until a wake-up event is detected. In this
mode, peripherals may be programmed to continue operating and can generate interrupts, causing the CPU
to exit from wait mode.
9.3.3.3 Doze Mode
Doze mode affects the processor in the same manner as wait mode, except that some peripherals define
individual operational characteristics in doze mode. Peripherals continuing to run and having the
capability of producing interrupts may cause the CPU to exit the doze mode and return to run mode.
Stopped peripherals restart operation on exit from doze mode, as defined for each peripheral.
9.3.3.4 Stop Mode
Stop mode affects the processor the same as the wait and doze modes, except that all clocks to the system
are stopped and the peripherals cease operation.
Stop mode must be entered in a controlled manner to ensure that any current operation is properly
terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation.
Entering stop mode disables the SDRAMC, including the refresh counter. If
SDRAM is used, code is required to ensure proper entry and exit from stop
mode. See
information.
9.3.4

Peripheral Behavior in Low-Power Modes

The following subsections specify the operation of each module while in and when exiting low-power
modes.
9.3.4.1 ColdFire Core
The ColdFire core disables during any low-power mode. No recovery time is required when exiting any
low-power mode.
9.3.4.2 Internal SRAM
The SRAM is disabled during any low-power mode. No recovery time is required when exiting any
low-power mode.
9.3.4.3 Clock Module
In wait and doze modes, the clocks to the CPU and SRAM stops and the system clocks to the peripherals
enable. Each module may disable the module clocks locally at the module level, or the module clocks may
be individually disabled by the PPMR registers (refer to
Registers (PPMHR0 and
Freescale Semiconductor
NOTE
Chapter 21, "SDRAM Controller (SDRAMC),"
PPMLR0)"). In stop mode, all clocks to the system stop.
for more
Section 9.2.4, "Peripheral Power Management
Power Management
9-9