Dspi Baud Rate And Clock Delay Generation - Freescale Semiconductor MCF54455 Reference Manual

POPNXTPTR equal to two means that the DSPI_RXFR2 contains the received SPI data that is returned
when DSPI_POPR is read. The POPNXTPTR field increments every time the DSPI_POPR is read.
POPNXTPTR rolls over every four frames on the MCU.
31.4.2.5.1 Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time an SPI frame is transferred
to the RX FIFO, the RX FIFO counter increments by one.
If the RX FIFO and shift register are full and a transfer is initiated, the DSPI_SR[RFOF] bit is asserted
indicating an overflow condition. Depending on the state of the DSPI_MCR[ROOE] bit, data from the
transfer that generated the overflow is ignored or shifted in to the shift register. If the ROOE bit is set,
incoming data is shifted in to the shift register. If the ROOE bit is cleared, the incoming data is ignored.
31.4.2.5.2 Draining the RX FIFO
Host software or the eDMA can remove (pop) entries from the RX FIFO by reading the DSPI_POPR. For
more information on DSPI_POPR, refer to
(DSPI_POPR)." A read of the DSPI_POPR decrements the RX FIFO counter by one. Attempts to pop data
from an empty RX FIFO are ignored, and the RX FIFO counter remains unchanged. The data returned
from reading an empty RX FIFO is undetermined.
When the RX FIFO is not empty, the RX FIFO drain flag, DSPI_SR[RFDF], is set. The RFDF bit is cleared
when the RX_FIFO is empty and the eDMA controller indicates that a read from DSPI_POPR is complete.
Alternatively, the RFDF bit can be cleared by software writing a 1 to it.
31.4.3

DSPI Baud Rate and Clock Delay Generation

The DSPI_SCK frequency and the delay values for serial transfer are generated by dividing the system
clock frequency by a prescaler and a scaler with the option of doubling the baud rate.
conceptually how the DSPI_SCK signal is generated.
System Clock
Figure 31-13. Communications Clock Prescalers and Scalers
31.4.3.1 Baud Rate Generator
The baud rate is the frequency of the serial communication clock (DSPI_SCK). The system clock is
divided by a baud rate prescaler (defined by DSPI_CTARn[PBR]) and baud rate scaler (defined by
DSPI_CTARn[BR]) to produce DSPI_SCK with the possibility of doubling the baud rate. The DBR, PBR,
and BR fields in the DSPI_CTARn select the frequency of DSPI_SCK using the following formula:
Freescale Semiconductor
Section 31.3.7, "DSPI Pop Receive FIFO Register
1
Prescaler
f
SYS/2
SCK baud rate = ------------------------------------------------- -
PBR Prescaler Value
DMA Serial Peripheral Interface (DSPI)
1+DBR
Scaler
1 + DBR

--------------------------------------- -
BR Scaler Value
Figure 31-13 shows
DSPI_SCK
Eqn. 31-1
31-25