Reset Sources - Freescale Semiconductor MCF54455 Reference Manual

Reset Controller Module
Field
7–6 Reserved, must be cleared.
5 Software reset flag. Indicates the software caused last reset.
SOFT 0 Last reset not caused by software
1 Last reset caused by software
4 Reserved, should be cleared.
3 Power-on reset flag. Indicates power-on reset caused the last reset.
POR 0 Last reset not caused by power-on reset
1 Last reset caused by power-on reset
2 External reset flag. Indicates that the last reset was caused by an external device or circuitry asserting the
EXT external RESET pin.
0 Last reset not caused by external reset
1 Last reset caused by external reset
1 Core watchdog timer reset flag. Indicates the core watchdog timer timeout caused the last reset.
WDRCORE 0 Last reset not caused by watchdog timer timeout
1 Last reset caused by watchdog timer timeout
0 Loss-of-lock reset flag. Indicates the last reset state was caused by a PLL loss of lock.
LOL 0 Last reset not caused by loss of lock
1 Last reset caused by a loss of lock
13.4 Functional Description
13.4.1

Reset Sources

Table 13-5 defines the reset sources and the signals driven by the reset controller.
Power on
External RESET pin (not stop mode)
External RESET pin (during stop mode)
Core Watchdog timer
Loss of lock
Software
To protect data integrity, a synchronous reset source is not acted upon by the reset control logic until the
end of the current bus cycle. Reset is then asserted on the next rising edge of the system clock after the
cycle is terminated. Internal byte, word, or longword writes are guaranteed to complete without data
corruption when a synchronous reset occurs. External writes, including longword writes to 16-bit ports,
are also guaranteed to complete.
13-4
Table 13-4. RSR Field Descriptions
Description
Table 13-5. Reset Source Summary
Source Type
Asynchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
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